DS64EV100-EVK National Semiconductor, DS64EV100-EVK Datasheet - Page 6

• Manufacturer Part Number: DS64EV100-EVK
• Description: KIT EVALUATION FOR DS64EV100
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DS64EV100-EVK

• Main Purpose: Interface, Cable Equalizer
• Utilized Ic / Part: DS64EV100
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

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DS64EV100 Applications
Information
The DS64EV100 is a programmable equalizer optimized for
operation up to 10 Gbps for backplane and cable applications.
EQUALIZER BOOST CONTROL
The equalizer channel supports eight programmable levels of
equalization boost, and is controlled by the Boost Set pins
(BST_[2:0]) in accordance with Table 1. The eight levels of
boost settings enables the DS64EV100 to address a wide
range of media loss and data rates.
GENERAL RECOMMENDATIONS
The DS64EV100 is a high performance circuit capable of de-
livering excellent performance. Careful attention must be paid
to the details associated with high-speed design as well as
providing a clean power supply. Refer to the LVDS Owner’s
Manual for more detailed information on high-speed design
tips to address signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The CML inputs and outputs must have a controlled differen-
tial impedance of 100Ω. It is preferable to route CML lines
Microstri
Length
p FR4
Trace
6 mil
(in)
10
15
20
25
30
40
0
5
TABLE 1. EQ Boost Control Table
Twin-AX
24 AWG
Length
Cable
(m)
10
0
2
3
4
5
6
7
Channel
3.2 GHz
Loss at
(db)
12.5
7.5
10
15
17
22
0
5
Loss at 5
GHz (dB)
Channel
10
14
18
21
24
30
0
6
FIGURE 5. Simplified Block Diagram
(Default)
[2, 1, 0]
BST_N
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
6
The equalizer channel consists of an equalizer stage, a lim-
iting amplifier, a DC offset correction block, and a CML driver
as shown in Figure 5.
exclusively on one layer of the board, particularly for the input
traces. The use of vias should be avoided if possible. If vias
must be used, they should be used sparingly and must be
placed symmetrically for each side of a given differential pair.
Route the CML signals away from other signals and noise
sources on the printed circuit board. See AN-1187 for addi-
tional information on LLP packages.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS64EV100 is provided with an adequate power supply.
First, the supply (V
nected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the V
a low inductance supply with distributed capacitance. Sec-
ond, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.01μF bypass ca-
pacitor should be connected to each V
capacitor is placed as close as possible to the DS64EV100.
Smaller body size capacitors can help facilitate proper com-
ponent placement. Additionally, three capacitors with capac-
itance in the range of 2.2 μF to 10 μF should be incorporated
in the power supply bypassing design as well. These capac-
itors can be either tantalum or an ultra-low ESR ceramic and
should be placed as close as possible to the DS64EV100.
DC COUPLING
The DS64EV100 supports both AC coupling with external ac
coupling capacitor, and DC coupling to its upstream driver, or
downstream receiver. With DC coupling, users must ensure
the input signal common mode is within the range of the elec-
trical specification V
with 50 Ω to V
DD
.
DD
ICMDC
) and ground (GND) pins should be con-
and the device output is terminated
DD
and GND planes create
DD
pin such that the
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