DS25MB100EVK National Semiconductor, DS25MB100EVK Datasheet
DS25MB100EVK
Specifications of DS25MB100EVK
Related parts for DS25MB100EVK
DS25MB100EVK Summary of contents
Page 1
DS25MB100-EVK Signal Conditioning Mux-Buffer Demo Board User Guide DS25MB100 EVK P.1 Rev 2.0 4/23/08 ...
Page 2
Introduction The DS25MB100 is a signal conditioning 2:1 multiplexer and 1:2 buffer designed to support port redundancy. Advanced signal conditioning features utilizing input equalization and output driver de-emphasis enable data communication over FR4 backplane or cable at 0.25 - 2.5Gb/s. ...
Page 3
Connection Diagram Pattern Generator D+ D- TRIG 1000mVpp differential Figure 1. Typical connection for evaluation of the DS25MB100 Power VCC JP17 3.3V ± 5% J16.3/4 GND JP20 0V J16.1/2 EQ controls EQL S6 EQL enables or disables Equalizer at the ...
Page 4
Logic control for data paths Following tables list the logic states of the control pins used to configure the data paths of the DS25MB100. More detailed information about pin functions and pin descriptions can be found in the DS25MB100 datasheet. ...
Page 5
Typical output waveforms The followings are typical eye diagrams of the DS25MB100 using demo board connected as shown in Figure 1. Figure 2a-b. Eye diagrams at 2.5 and 1.25 Gb/s, PRBS7 pattern, Pre-emphasis=0dB Figure 3a-b. Eye diagrams at 2.5 and ...
Page 6
DS25MB100-EVK board schematic DS25MB100 EVK P.6 Rev 2.0 4/23/08 ...