LMH1982SQEEVAL National Semiconductor, LMH1982SQEEVAL Datasheet - Page 26
LMH1982SQEEVAL
Manufacturer Part Number
LMH1982SQEEVAL
Description
BOARD EVAL FOR LMH1982SQE
Manufacturer
National Semiconductor
Datasheets
1.LMH1982SQENOPB.pdf
(34 pages)
2.LMH1982SQEEVAL.pdf
(20 pages)
3.LMH1982SQEEVAL.pdf
(12 pages)
Specifications of LMH1982SQEEVAL
Main Purpose
Video, Video Processing
Utilized Ic / Part
LMH1982SQE
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
www.national.com
9.1 Genlock And Input Reference Control Registers
Register 00h
Bits 2-0: H Input Error Max Count (H_ERROR)
The H_ERROR bits control the reference detector's error
threshold, which determines the maximum number of missing
H sync pulses before indicating a LOR. See section 6.1.1
Programming the Loss of Reference (LOR) Threshold.
Bit 3: Holdover on Loss of Reference (HOLDOVER)
The HOLDOVER bit controls the operating mode when a loss
of reference occurs. See section 3.2.2 Loss of Reference
(LOR).
Bit 4: Reference Select (RSEL)
The RSEL bit selects either REF_A or REF_B inputs as the
reference to genlock the outputs when I
If PIN6_OVRD = 1 (register 02h), then reference selection
must be controlled by programming RSEL, regardless of
I
reference selection is controlled using the REF_SEL input pin
and the RSEL bit is ignored.
Bit 5: Reference Select Control via I
By programming I
trolled either via I
RSEL.
REF_SEL input pin.
Note: If PIN6_OVRD = 1, then reference selection must be controlled by
Bit 6: Mode Select (GNLK)
The GNLK bit selects the operating mode when I
1. See section 3.0 MODES OF OPERATION.
If I
using the GENLOCK input pin and the GNLK bit will be ig-
nored.
Bit 7: Mode Select via I
By programming I
trolled either via I
GNLK.
input pin.
9.2 Genlock Status And Lock Control Register
Register 01h
Bit 0: Reference Status (REF_VALID)
REF_VALID is a read-only bit and indicates the presence or
loss of reference on the selected reference port in Genlock
mode. The NO_REF output flag is an inverted copy of
REF_VALID. See section 6.1 Reference Detection.
In Free Run mode, REF_VALID will be set to 0 to indicate the
absence of any input pulses at the selected HREF port.
2
C_RSEL. When PIN6_OVRD = 0 and I
RSEL = 0: Select REF_A inputs.
RSEL = 1: Select REF_B inputs.
I
I
GNLK = 0: Selects Free Run mode.
GNLK = 1: Selects Genlock mode.
I
I
REF_VALID = 0: Indicates loss of reference (LOR).
REF_VALID = 1: Indicates valid reference.
2
2
2
2
2
C_GNLK = 0, then the operating mode will be controlled
C_RSEL = 1: Control reference selection by programming
C_RSEL = 0: Control reference selection via the
C_GNLK = 1: Control mode selection by programming
C_GNLK = 0: Control mode selection via the GENLOCK
programming RSEL regardless of I
2
2
2
C or the REF_SEL input pin.
C or the GENLOCK input pin.
C_RSEL, reference selection can be con-
2
C_GNLK, mode selection can be con-
2
C (I
2
C_GNLK)
2
C_RSEL.
2
C (I
2
C_RSEL = 1.
2
C_RSEL = 0, then
2
C_RSEL)
2
C_GNLK =
26
Bit 1: SD Clock PLL Lock Status (SD_LOCK)
SD_LOCK is a read-only bit and indicates PLL lock status of
the selected SD clock. See section 6.2 PLL Lock Detection.
Bit 2: HD Clock PLL Lock Status (HD_LOCK)
HD_LOCK is a read-only bit and indicates PLL lock status of
the selected HD clock. See section 6.2 PLL Lock Detection.
Bits 7-3: Lock Control (LOCK_CTRL)
LOCK_CTRL controls the phase error threshold of PLL 1's
lock detector. A larger value for LOCK_CTRL will yield shorter
lock indication time (although not actual lock time) at the ex-
pense of higher output phase error when lock is initially indi-
cated, whereas a smaller value will yield the opposite effect.
See section 6.2.1 Programming the PLL Lock Threshold.
9.3 Input Control Register
Register 02h
Bit 0: VREF_B Input Signal Polarity (POL_VB)
This bit should be programmed to match the input signal po-
larity at the VREF_B input pin.
Bit 1: HREF_B Input Signal Polarity (POL_HB)
This bit should be programmed to match the input signal po-
larity at the HREF_B input pin. The positive edge of the output
clock will be phase locked to the active edge of the H sync
input signal.
Bit 2: VREF_A Input Signal Polarity (POL_VA)
This bit should be programmed to match the input signal po-
larity at the VREF_A input pin.
Bit 3: HREF_A Input Signal Polarity (POL_HA)
This bit should be programmed to match with the input signal
polarity at HREF_A input pin. The positive edge of the output
clock will be phase locked to the active edge of the H sync
input signal.
Bit 4: 27 MHz Reference Control (27M_REF)
Instead of an H sync signal, a 27 MHz clock signal can be
applied to the selected HREF input to phase lock the output
clocks. If a 27 MHz clock is used as a reference, then a value
of 1 should be programmed to 27M_REF, REF_DIV_SEL,
and FB_DIV.
REF_DIV_SEL =1 and FB_DIV = 1
Note: Because the loop gain, K, for 27 MHz clock input is much larger than
SD_LOCK = 0: Indicates loss of lock.
SD_LOCK = 1: Indicates valid lock.
HD_LOCK = 0: Indicates loss of lock.
HD_LOCK = 1: Indicates valid lock.
POL_VB = 0: Negative polarity or active low signal.
POL_VB = 1: Positive polarity or active high signal.
POL_HB = 0: Negative polarity or active low signal.
POL_HB = 1: Positive polarity or active high signal.
POL_VA = 0: Negative polarity or active low signal.
POL_VA = 1: Positive polarity or active high signal.
POL_HA = 0: Negative polarity or active low signal.
POL_HA = 1: Positive polarity or active high signal.
27M_REF = 0: H sync input signal.
27M_REF = 1: 27 MHz clock input signal. Also, set
for an H sync input (due to the large difference in FB_DIV), the loop