DS50PCI401EVK National Semiconductor, DS50PCI401EVK Datasheet

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DS50PCI401EVK

Manufacturer Part Number
DS50PCI401EVK
Description
EVAL KIT PCI EXPRESS SMA
Manufacturer
National Semiconductor
Datasheets

Specifications of DS50PCI401EVK

Main Purpose
Interface, Transceiver, PCI Express
Embedded
No
Utilized Ic / Part
DS50PCI401
Primary Attributes
5 Gbps Quad Lane Bidirectional Buffer & Equalizer
Secondary Attributes
3.3V LVCMOS Input Tolerant for SMBus Interface
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
© 2010 National Semiconductor Corporation
2.5 Gbps / 5.0 Gbps 4 Lane PCI Express Repeater with
Equalization and De-Emphasis
General Description
The DS50PCI401 is a low power, 4 lane bidirectional buffer/
equalizer designed specifically for PCI Express Gen1 and
Gen2 applications. The device performs both receive equal-
ization and transmit de-emphasis, allowing maximum flexibil-
ity of physical placement within a system. The receiver is
capable of opening an input eye that is completely closed due
to inter-symbol interference (ISI) induced by the interconnect
medium.
The transmitter de-emphasis level can be set by the user de-
pending on the distance from the DS50PCI401 to the PCI
Express endpoint. The DS50PCI401 contains PCI Express
specific functions such as Transmit Idle, RX Detection, and
Beacon signal pass through.
The device will change the load impedance on its input pins
based on the state of RXDETA/B inputs detection. An internal
rate detection circuit is included to detect if an incoming data
stream is at Gen2 data rates, and adjusts the de-emphasis
on it's output accordingly. The signal conditioning provided by
the device allows systems to upgrade from Gen1 data rates
to Gen2 without reducing their physical reach. This is true for
FR4 applications such as backplanes, as well as cable inter-
connect.
Typical Application
300604
DS50PCI401
Features
Input and Output signal conditioning increases PCIe reach
in backplanes and cables
0.09 UI of residual deterministic jitter at 5Gbps after 42” of
FR4 (with Input EQ)
0.11 UI of residual deterministic jitter at 5Gbps after 7m of
PCIe Cable (with Input EQ)
0.09 UI of residual deterministic jitter at 5Gbps with 28” of
FR4 (with Output DE)
0.13 UI of residual deterministic jitter at 5Gbps with 7m of
PCIe Cable (with Output DE)
Adjustable Transmit VOD 800 to 1200mVp-p
Automatic power management on an individual lane basis
via SMBus
Adjustable electrical idle detect threshold.
Data rate optimized 3-stage equalization to 26 dB gain
Data rate optimized 6-level 0 to 12 dB transmit de-
emphasis
Flow-thru pinout in 10mmx5.5mm 54-pin leadless LLP
package
Single supply operation at 2.5V
>6kV HBM ESD rating
-10 to 85°C operating temperature range
30060480
October 29, 2010
www.national.com

Related parts for DS50PCI401EVK

DS50PCI401EVK Summary of contents

Page 1

... Gen1 data rates to Gen2 without reducing their physical reach. This is true for FR4 applications such as backplanes, as well as cable inter- connect. Typical Application © 2010 National Semiconductor Corporation DS50PCI401 Features ■ Input and Output signal conditioning increases PCIe reach in backplanes and cables ■ ...

Page 2

Block Diagram - Detail View Of Channel ( www.national.com 2 30060486 ...

Page 3

Pin Diagram Ordering Information NSID Qty DS50PCI401SQ Tape & Reel Supplied As 2,000 Units DS50PCI401SQE Tape & Reel Supplied As 250 Units DS50PCI401 Pin Diagram 54 lead Spec NOPB NOPB 3 30060492 Package SQA54A SQA54A www.national.com ...

Page 4

Pin Descriptions Pin Name Pin Number Differential High Speed I/O's IA_0+, IA_0- , 10, 11 IA_1+, IA_1-, 12, 13 IA_2+, IA_2-, 15, 16 IA_3+, IA_3- 17, 18 OA_0+, OA_0-, 35, 34 OA_1+, OA_1-, 33, 32 OA_2+, OA_2-, 31, 30 OA_3+, ...

Page 5

Pin Name Pin Number DEMA0, DEMA1 49, 50 DEMB0, DEMB1 53, 54 RATE 21 Control Pins — Both Modes (LVCMOS) RXDETA,RXDETB 22,23 PRSNT 52 ENRXDET 26 TXIDLEA,TXIDLEB 24,25 Analog SD_TH 27 Power VDD 9, 14,36, 41, 51 GND DAP Notes: ...

Page 6

Functional Description The DS50PCI401 is a low power media compensation 4 lane repeater optimized for PCI Express Gen 1 and Gen 2 media including lossy FR-4 printed circuit board backplanes and balanced cables. The DS50PCI401 operates in two modes: Pin ...

Page 7

RATE DEM1 DEM0 Typical De- Emphasis Level 1 Reserved, don't use F=Float (don't drive pin - (each float pin has an internal 50K Ohm resistor to VDD and GND). Enhanced DE Pulse width provides additional de-emphasis on second ...

Page 8

USING RXDETA PCIe ENVIRONMENT In order for upstream and downstream PCIe subsystems to communicate in a cabling environment, the PCIe specification includes several auxiliary or sideband signals to manage sys- tem-level functionality or implementation. Similar methods are used ...

Page 9

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD) LVCMOS Input/Output Voltage CML Input Voltage CML Input Current LPDS Output Voltage Analog (SD_TH) Junction Temperature Storage Temperature Lead Temperature Range Soldering (4 sec ...

Page 10

Symbol Parameter CML RECEIVER INPUTS (IN_n+, IN_n package plus Si RX-DIFF differential return loss RL Common mode Rx RX-CM return loss common mode RX-DC impedance differential RX-DIFF-DC impedance V Differential Rx peak ...

Page 11

Symbol Parameter V Absolute Delta of DC TX-CM-DC- LINE-DELTA Common Mode Voltage between Tx+ and Tx- T Max time to transition to TX-IDLE-SET-TO -IDLE valid diff signaling after leaving Electrical Idle T Max time to transition to TX-IDLE-TO -DIFF-DATA valid ...

Page 12

Symbol Parameter DE-EMPHASIS Residual Deterministic Jitter at 5 Gbps DJD1 Residual Deterministic Jitter at 2.5 Gbps DJD2 Residual Deterministic Jitter at 5 Gbps DJD3 Residual Deterministic Jitter at 2.5 Gbps DJD4 Note 1: “Absolute Maximum Ratings” indicate limits beyond which ...

Page 13

Electrical Characteristics — Serial Management Bus Interface Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter SERIAL BUS INTERFACE DC SPECIFICATIONS V Data, Clock Input Low Voltage IL V Data, Clock Input High Voltage IH I Current ...

Page 14

Timing Diagrams www.national.com FIGURE 3. CML Output Transition Times FIGURE 4. Propagation Delay Timing Diagram FIGURE 5. Idle Timing Diagram 14 30060402 30060403 30060404 ...

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FIGURE 6. Input and Output Return Loss Setup FIGURE 7. SMBus Timing Parameters 15 30060454 30060494 www.national.com ...

Page 16

System Management Bus (SMBus) and Configuration Registers The System Management Bus interface is compatible to SM- Bus 2.0 physical layer specification. ENSMB must be pulled high to enable SMBus mode and allow access to the config- uration registers. The DS50PCI401 ...

Page 17

Write 32'h to address 0x47. The following IDLE status should be observable on the ex- ternal pins: pin 19 – CH0 with CH2, pin 20 – CH1 with CH3, pin 46 – CH4 with CH6, pin 47 – CH5 with ...

Page 18

Address Register Name Bit (s) Field 0x00 Reset 7:1 0 0x01 PWDN Channels 7:0 0x02 PWDN Control 7:1 0 0x08 Pin Control Override 7 1:0 www.national.com TABLE 6. SMBus Register Map Type Default Description Reserved R/W 0x00 ...

Page 19

CH0 - CHB0 7:6 IDLE RATE Select 0x0F CH0 - CHB0 7:6 EQ Control 5:0 0x10 CH0 - CHB0 7 VOD Control 6:0 0x11 CH0 - CHB0 7:0 DE Control 0x12 CH0 - CHB0 ...

Page 20

CH1 - CHB1 7:6 IDLE RATE Select 0x16 CH1 - CHB1 7:6 EQ Control 5:0 0x17 CH1 - CHB1 7 VOD Control 6:0 0x18 CH1 - CHB1 7:0 DE Control 0x19 CH1 - CHB1 ...

Page 21

CH2 - CHB2 7:6 IDLE RATE Select 0x1D CH2 - CHB2 7:6 EQ Control 5:0 0x1E CH2 - CHB2 7 VOD Control 6:0 0x1F CH2 - CHB2 7:0 DE Control 0x20 CH2 - CHB2 ...

Page 22

CH3 - CHB3 7:6 IDLE RATE Select 0x24 CH3 - CHB3 7:6 EQ Control 5:0 0x25 CH3 - CHB3 7 VOD Control 6:0 0x26 CH3 - CHB3 7:0 DE Control 0x27 CH3 - CHB3 ...

Page 23

CH4 - CHA0 7:6 IDLE RATE Select 0x2C CH4 - CHA0 7:6 EQ Control 5:0 0x2D CH4 - CHA0 7 VOD Control 6:0 0x2E CH4 - CHA0 7:0 DE Control 0x2F CH4 - CHA0 ...

Page 24

CH5 - CHA1 7:6 IDLE RATE Select 0x33 CH5 - CHA1 7:6 EQ Control 5:0 0x34 CH5 - CHA1 7 VOD Control 6:0 0x35 CH5 - CHA1 7:0 DE Control 0x36 CH5 - CHA1 ...

Page 25

CH6 - CHA2 7:6 IDLE RATE Select 0x3A CH6 - CHA2 7:6 EQ Control 5:0 0x3B CH6 - CHA2 7 VOD Control 6:0 0x3C CH6 - CHA2 7:0 DE Control 0x3D CH6 - CHA2 ...

Page 26

CH7 - CHA3 7:6 IDLE RATE Select 0x41 CH7 - CHA3 7:6 EQ Control 5:0 0x42 CH7 - CHA3 7 VOD Control 6:0 0x43 CH7 - CHA3 7:0 DE Control 0x44 CH7 - CHA3 ...

Page 27

Applications Information GENERAL RECOMMENDATIONS The DS50PCI401 is a high performance circuit capable of delivering excellent performance. Careful attention must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer to the information ...

Page 28

Typical Performance Eye Diagrams and Curves DS50PCI401 Return Loss FIGURE 10. Transmitter Return Loss Mask for 5.0 Gbps www.national.com FIGURE 9. Receiver Return Loss Mask for 5.0 Gbps 28 30060450 30060451 ...

Page 29

Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS50PCI401SQ (Tape and Reel 2000 units) Order Number DS50PCI401SQE (Tape and Reel 250 units) (See AN-1187 for PCB Design and Assembly Recommendations) NS Package Number SQA54A 29 www.national.com ...

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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...

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