MAX11068EVKIT+ Maxim Integrated Products, MAX11068EVKIT+ Datasheet - Page 55

• Manufacturer Part Number: MAX11068EVKIT+
• Description: KIT SMART BATT MEASUREMENT 12CH
• Manufacturer: Maxim Integrated Products

Specifications of MAX11068EVKIT+

• Main Purpose: Power Management, Battery Monitor, Car
• Utilized Ic / Part: MAX11068
• Primary Attributes: Monitors Current, Voltage, Temperature
• Secondary Attributes: 1 ~ 12 Cell- Li-Ion, 1 ~ 12 Cell- NiMH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -

Each port contains a bidirectional SDA pin with managed
internal pullup drivers. The SCL pin for the lower slave
port is an input only, while the upper port master SCL pin
has a 1kω pullup driver. Glitch filters and Schmitt trig-
ger buffers are present on the input signals to minimize
communication errors. The alarm signal input is Schmitt
trigger with a current and voltage-clamping circuit while
the lower port alarm output is a push-pull driver. Each
port is designed to operate in an AC- or DC-coupled
bus configuration. All signal pins have a weak 150kI
pullup to their respective VDD supply to establish the
customary idle state of the I
ing description assumes the AC-coupled circuit shown
in Figure 28.
Since the SDA signal path must be bidirectional, manag-
ing the handoff of roles between transmitting nodes and
receiving nodes is critical to data integrity. At the same
time, the bus must be able to drive a certain capacitive
load size to maintain specified timing performance. To
meet these requirements, a managed resistance pullup
system with a strong pulldown driver is implemented in
both the master and slave blocks. When the SDA pin for
a given block is the driver of a signal edge on the line,
it first connects both a 1kI resistor and a 50kI resistor
from its VDD supply to SDA to initiate the active edge.
This strong pullup provides extra drive strength initially
to speed the charging of the parasitic capacitances
connected to the SDA pin and is active for the time
period t
eter, C
may be present on the SDA pin so that the SDA voltage
level transitions to within 70% of its nominal value within
the time period of the one-shot active edge. When the
one-shot period is over, the 1kI resistor is disconnected
and the 50kI pullup remains to complete the active
1_TAU,
ONE-SHOT
specifies the maximum capacitance that
, which is typically 250ns. A param-
12-Channel, High-Voltage Sensor, Smart
2
C bus. The following operat-
Data-Acquisition Interface
edge transition. This weaker pullup continues to actively
drive the line until the particular SDA pin is no longer in a
transmitting state. During the acknowledge bit time, the
SDA pin that had been receiving data is able to use its
pulldown driver to overcome the 50kI pullup driven by
the transmitting device and successfully acknowledge
the transmission. Internal circuitry prevents the coupling
capacitors from accumulating charge and causing a DC
drift on the signals.
When the host or a device master drives the AC-coupled
SCL line with a signal edge, the high-frequency edge
passes to the slave side of the coupling capacitor where
it is received at the SCL input pin. Since the 150kI pas-
sive pullup resistor value is large, the time constant of
the pullup’s effect during communication when paired
with the typical 3.3nF AC-coupling capacitor is large
compared to the specified range of the I
Using resistor values lower than 150kI or changing
the coupling-capacitor value could affect the margin of
the bus timing specifications at some communication
frequencies. Since the SCL signal is unidirectional, no
internal pullup resistor manipulation for the driver circuit
is necessary. As with the SDA pins, internal circuitry pre-
vents the coupling capacitors from accumulating charge.
The MAX11068 supports seven different commands.
There are two main cycle formats, one for READALL and
the other for the rest of the commands. Several com-
mands require the host to send a PEC byte or for the
chain to send a PEC byte to the host. This is an imple-
mentation of the SMBus PEC algorithm, which is a CRC-8
process where all bits in the packet are cycled through
the CRC engine. Table 35 is the I
I
2
C Command Summary
2
C command list.
2
C clock period.
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