MAX11068EVKIT+ Maxim Integrated Products, MAX11068EVKIT+ Datasheet - Page 67

• Manufacturer Part Number: MAX11068EVKIT+
• Description: KIT SMART BATT MEASUREMENT 12CH
• Manufacturer: Maxim Integrated Products

Specifications of MAX11068EVKIT+

• Main Purpose: Power Management, Battery Monitor, Car
• Utilized Ic / Part: MAX11068
• Primary Attributes: Monitors Current, Voltage, Temperature
• Secondary Attributes: 1 ~ 12 Cell- Li-Ion, 1 ~ 12 Cell- NiMH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -

Table 37. Data Check Byte Definition
For 20 modules with a 200kbps I
it takes approximately 2.0ms to perform a READALL or
ROLLCALL command for one register. Since there are
16 frequently read registers, it would take 32ms to per-
form a complete read of all devices for those registers.
If an additional nine configuration registers are included,
then 50ms are required. A 100kbps I
fast enough to perform this task in a reasonable amount
of time.
WRITEALL consumes the following amount of time
based on the number of bits in the command protocol,
and the number of modules in the SMBus ladder:
For 20 modules with a 200kbps I
is approximately 250Fs to perform a WRITEALL com-
mand for one register.
The MAX11068 uses the SMBus PEC mechanism for
maintaining data integrity. PEC verifies stage-to-stage
communication both in the write and read directions.
During any write transaction, a device does not execute
the write command internally unless the PEC is received
successfully by the lower port. The host can easily
ignore the PEC byte from a READALL command if the
host does not intend to support PEC for read transac-
tions. The only verification of a successful write trans-
action that the host receives is through the ACK bit
following the PEC byte returned from the first device in
the SMBus ladder. This bit indicates whether the first
t
WRITEALL
BIT
7
6
5
4
3
2
1
0
=
+
(
5 8 bits 5 bits 2 bits
(
N
×
MODULES
12-Channel, High-Voltage Sensor, Smart
Packet-Error Checking (PEC)
PECERR
NAME
ALRM
0
0
0
0
0
0
+
−
1
)
+
×
2
C master data rate, this
t
Set if the device is in an alarm condition, meaning the ALRML pin is high.
Unused, read as 0.
Unused, read as 0.
Unused, read as 0.
Unused, read as 0.
Unused, read as 0.
Unused, read as 0.
During a READALL command, the slave returns PECERR = 0 if the master received a valid
PEC. The slave returns PECERR = 1 if the master received an invalid PEC or the master
received PECERR = 1. In this way, the system can verify communication not only one layer
at a time, but also across all layers.
LEVEL SHIFT DELAY
2
C master data rate,
2
C master would be
)
×
−
t
SCL
−
Data-Acquisition Interface
device received a valid write command. The success
of the write command further up the chain is unknown
to the host. If verification is critical, the host should fol-
low up any write command with a READALL to verify
the write by checking the register that was updated or
the ALRTPEC bit of the STATUS register. The PEC alert
may also be enabled to trigger an alarm through the
ALRMPEC bit of the ADCCFG register (address 0x08). If
no alarms are present following the write command, the
host can infer that the write command was successful to
all attached devices.
To support PEC, the host must implement a CRC-8 algo-
rithm to perform calculations necessary for the PEC byte.
The CRC-8 polynomial is:
All bytes including addresses, command codes, data,
and for READALL, the data check byte should be pro-
cessed by the CRC-8 algorithm as input bytes. START,
repeated START, STOP, and ACK/NACK bits are not
included in the calculation. The bits should be pro-
cessed in the order they are received with MSB first.
The logic implementation can be described as follows.
First, the CRC is initialized to zero for a new calculation.
For each input byte, the byte is first XORed with the CRC
value. This byte is called the remainder. The remainder
is left shifted by 1 bit and is sent to a mux as itself or
XORed with the 8 least significant bits of the polynomial
representation. The bit lost in the left-shift operation is
able to be ignored because either it is a zero, or if it is a
1, it would be XORed with the most significant bit of the
polynomial representation to yield a 0. Therefore, only
DESCRIPTION
C(x) x
=
8
+
x
2
+ +
x 1
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