ADC12DL066EVAL National Semiconductor, ADC12DL066EVAL Datasheet
ADC12DL066EVAL
Specifications of ADC12DL066EVAL
Related parts for ADC12DL066EVAL
ADC12DL066EVAL Summary of contents
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... An evaluation board is available to ease the evalua- tion process. Connection Diagram TRI-STATE® registered trademark of National Semiconductor Corporation. © 2008 National Semiconductor Corporation Features ■ Choice of Binary or 2’s complement output format ■ ...
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... Ordering Information Industrial (−40°C ADC12DL066CIVS ADC12DL066EVAL Block Diagram www.national.com ≤ ≤ Package T +85° Pin TQFP Evaluation Board 2 20055202 ...
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Pin Descriptions and Equivalent Circuits Pin No. Symbol ANALOG I/O V A− B− IN REF 11 INT/EXT REF ...
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Pin No. Symbol 24–29 DA0–DA11 34–39 42–47 DB0–DB11 52–57 ANALOG POWER 9, 18, 19, 62 10, 17, AGND 20, 61, 64 DIGITAL POWER V 33 32, 49 DGND V 30, 51 ...
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... Absolute Maximum Ratings (Notes Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications – Voltage on Any Input or Output Pin Input Current at Any Pin (Note 3) Package Input Current (Note 3) Package Dissipation 25°C A ESD Susceptibility ...
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Symbol Parameter DYNAMIC CONVERTER CHARACTERISTICS FPBW Full Power Bandwidth SNR Signal-to-Noise Ratio SINAD Signal-to-Noise and Distortion ENOB Effective Number of Bits THD Total Harmonic Distortion H2 Second Harmonic Distortion H3 Third Harmonic Distortion SFDR Spurious Free Dynamic Range IMD Intermodulation ...
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DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V 0V, INT/EXT REF pin = +3.3V, V apply for all ...
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Symbol Parameter t Aperture Jitter AJ t Clock Edge to Data Transition HOLD t Data outputs into Hi-Z Mode DIS t Data Outputs Active after Hi-Z Mode EN t Power Down Mode Exit Cycle PD Note 1: Absolute Maximum Ratings ...
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Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conver- sion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. ...
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Timing Diagram Transfer Characteristic www.national.com Output Timing FIGURE 1. Transfer Characteristic 10 20055209 20055210 ...
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Typical Performance Characteristics otherwise stated DNL DNL vs DNL vs. f CLK +3.3V +2.5V 20055218 20055221 20055219 MHz MHz unless CLK IN ...
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DNL vs. Clock Duty Cycle DNL vs. Temperature SNR, SINAD, SFDR vs. V www.national.com 20055220 20055222 SNR, SINAD, SFDR vs 20055233 12 INL vs. Clock Duty Cycle 20055225 INL vs. Temperature 20055227 CLK 20055228 ...
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SNR, SINAD, SFDR vs. CLOCK DUTY CYCLE SNR, SINAD, SFDR vs. V REF Distortion vs SNR, SINAD, SFDR vs. V 20055229 SNR, SINAD, SFDR vs. Temperature 20055231 Distortion vs. F 20055240 13 CM 20055232 20055234 CLK 20055236 www.national.com ...
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Distortion vs. Clock Duty Cycle Distortion vs vs www.national.com 20055237 REF 20055238 DR 20055243 14 Distortion vs 20055239 Distortion vs. Temperature 20055241 SPECTRAL PLOT MHz IN 20055261 ...
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SPECTRAL PLOT MHz IN 20055262 IMD PERFORMANCE 9.6 MHz 10.2 MHz IN 20055263 www.national.com ...
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Functional Description Operating on a single +3.3V supply, the ADC12DL066 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The user has the choice of ...
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FIGURE 2. Expected Input Signal Range For single frequency sine waves with angular errors of less π than 45° ( /4) between the two inputs, the full scale error in LSB can be described as approximately (n-1) ...
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FIGURE 4. Application Circuit using Transformer or Differential Op-Amp Drive Circuit FIGURE 5. Differential Drive Circuit using a fully differential amplifier. For undersampling applications, the RC pole should be set at about 1 times the maximum input frequency ...
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V supply voltage. The nominal V A ally be about V /2, but V A and V REF source as long as no d.c. current is drawn from either of CM these pins. 2.0 DIGITAL ...
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To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by connecting buffers (74AC541, for example) between the ADC outputs and any other circuitry. Only one driven input should be con- ...
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Since digital switching transients are composed largely of high frequency components, total ground plane copper weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area is more important than is total ...
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Operating with the reference pins outside of the specified range. As mentioned in Section 1.2, V range of ...
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Physical Dimensions inches (millimeters) unless otherwise noted 64-Lead TQFP Package Ordering Number ADC12DL066CIVS NS Package Number VECO64A 23 www.national.com ...
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