LM4930LQBD National Semiconductor, LM4930LQBD Datasheet - Page 30

• Manufacturer Part Number: LM4930LQBD
• Description: BOARD EVALUATION LM4930LQ
• Manufacturer: National Semiconductor
• Series: Boomer®r

Specifications of LM4930LQBD

• Amplifier Type: Class AB
• Output Type: 1-Channel (Mono) with Stereo Headphones
• Max Output Power X Channels @ Load: 1W x 1 @ 8 Ohm; 27mW x 2 @ 32 Ohm
• Voltage - Supply: 2.6 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Board Type: Fully Populated
• Utilized Ic / Part: LM4930
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Application Information
ADR SELECT (S1)
Jumper IN = LOW
CONFIG)
Jumper OUT = HIGH
CONFIG)
Onboard MCLK Select (S2)
Jumper IN = Onboard MCLK
Jumper OUT = External MCLK
LM4930ITL DEMO BOARD OPERATION
The LM4930ITL demo board is a complete evaluation plat-
form, designed to give easy access to the control pins of the
part and comprise all the necessary external passive com-
ponents. Besides the separate analog (J9) and digital (J10)
supply connectors, the board features seven other major
input and control blocks: a two wire interface bus (J1) for the
control lines, a PCM interface bus (P1-P4) for voiceband
digital audio, an I2S interface bus (J2) for full-range digital
audio, an analog mic jack input (J3) for connection to an
external microphone, a BTL mono output (J7) for connection
to an external speaker, a stereo headphone output (J8), and
an external MCLK input (P5) for use in place of the crystal on
the demoboard.
Two-wire Interface Bus (J1)
This is the main control bus for the LM4930. It is a two-wire
interface with an SDA line (data) and SCL line (clock). Each
transmission from the baseband controller to the LM4930 is
given MSB first and must follow the timing intervals given in
the Electrical Characteristics section of the datasheet to
create the start and stop conditions for a proper transmis-
sion. The start condition is detected if SCL is high on the
falling edge of SDA. The stop condition is detected if SCL is
high on the rising edge of SDA. Repeated start signals are
handled correctly. Data is then transmitted as shown in
Figure 2. After the start condition has been achieved the chip
address is sent, followed by a set write bit, wait for ack (SDA
will be pulled low by LM4930), data bits 15-8, wait for ACK
(SDA will be pulled low by LM4930), data bits 7-0, wait for
ACK (SDA will be pulled low by LM4930)and finally the stop
condition is given.
Control interface responds to addresses 001000b (BASICCONFIG), 0010001b (VOICETESTCONFIG)), and 0010010b (GAIN-
Control interface responds to addresses 111000b (BASICCONFIG), 1110001b (VOICETESTCONFIG)), and 1110010b (GAIN-
Pin
1
2
1
2
Pin
1
2
(Continued)
MCLK/XTAL_IN (P5) (Continued)
Misc Jumpers and Headers
HP Sense Out (J6)
IRQ (J4)
30
This same sequence follows for any control bus transmis-
sion to the LM4930. The chip address is hardwire selected
by the ADR Select pin which may be jumpered high or low
with its application at S1 on the demo board. The chip
address is then given as a combination of the identifying bits
for the LM4930 plus the 2-bit address of the desired control
register (00b = BasicConfig, 01b = VoicetestConfig, 10b =
GainConfig). Acceptable addresses are shown here in Table
1.
Data is sampled only if the address is in range and the R/W
bit is clear. Data for each register is given in the System
Control Registers section of the datasheet. National Semi-
conductor also features a special control board for quick
evaluation of the LM4930 demo board with your PC. This is
a serial control interface board, complete with header com-
Address Bits
ADR = 0
6
0
0
0
ADR = 1
1
1
1
Table 1. LM4930 Control Bus Addresses
5
0
0
0
1
1
1
4
1
1
1
1
1
1
Function
AGND
HPSense_Out
DGND
MCLK/XTAL_IN
Function
DGND
IRQ
3
0
0
0
0
0
0
2
0
0
0
0
0
0
Register
Address
1
0
0
1
0
0
1
0
0
1
0
0
1
0