LM4844TLEVAL National Semiconductor, LM4844TLEVAL Datasheet - Page 18

• Manufacturer Part Number: LM4844TLEVAL
• Description: BOARD EVALUATION LM4844TL
• Manufacturer: National Semiconductor
• Series: Boomer®r

Specifications of LM4844TLEVAL

• Amplifier Type: Class AB
• Output Type: 2-Channel (Stereo) with Stereo Headphones
• Max Output Power X Channels @ Load: 1.2W x 2 @ 8 Ohm; 80mW x 2 @ 32 Ohm
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Board Type: Fully Populated
• Utilized Ic / Part: LM4844
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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I
The LM4844 uses a serial bus, which conforms to the I
protocol, to control the chip's functions with two wires: clock
(SCL) and data (SDA). The clock line is uni-directional. The
data line is bi-directional (open-collector). The maximum
clock frequency specified by the I
this discussion, the master is the controlling microcontroller
and the slave is the LM4844.
The I
pin. The LM4844's two possible I
form 111110X
and X
address a number of chips in a system, the LM4844's chip
address can be changed to avoid any possible address con-
flicts.
The bus format for the I
bus format diagram is broken up into six major sections:
The "start" signal is generated by lowering the data signal
while the clock signal is high. The start signal will alert all de-
vices attached to the I
against their own address.
The 8-bit chip address is sent next, most significant bit first.
The data is latched in on the rising edge of the clock. Each
address bit must be stable while the clock level is high.
After the last bit of the address bit is sent, the master releases
the data line high (through a pull-up resistor). Then the master
sends an acknowledge clock pulse. If the LM4844 has re-
ceived the address correctly, then it holds the data line low
during the clock pulse. If the data line is not held low during
the acknowledge clock pulse, then the master should abort
the rest of the data transfer to the LM4844.
The 8 bits of data are sent next, most significant bit first. Each
data bit should be valid while the clock level is stable high.
After the data byte is sent, the master must check for another
acknowledge to see if the LM4844 received the data.
If the master has more data bytes to send to the LM4844, then
the master can repeat the previous two steps until all data
bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data
signal goes high while the clock signal is high. The data line
should be held high when not in use.
I
The LM4844's I
I
level set by the I
that of the main power supply pin V
logic levels for the I
troller or microprocessor that is operating at a lower supply
voltage than the main battery of a portable system.
NATIONAL 3D ENHANCEMENT
The LM4844 features a 3D audio enhancement effect that
widens the perceived soundstage from a stereo audio signal.
The 3D audio enhancement improves the apparent stereo
channel separation whenever the left and right speakers are
too close to one another, due to system size constraints or
equipment limitations.
An external RC network, shown in Figure 1, is required to en-
able the 3D effect. There are separate RC networks for both
the stereo loudspeaker outputs as well as the stereo head-
phone outputs, so the 3D effect can be set independently for
each set of stereo outputs.
The amount of the 3D effect is set by the R
creasing the value of R
2
2
2
C COMPATIBLE INTERFACE
C INTERFACE POWER SUPPLY PIN (I
CV
DD
2
C address for the LM4844 is determined using the ADR
1
= 1, if ADR is logic high. If the I
pin. The LM4844's I
1
0 (binary), where X
2
2
CV
C interface is powered up through the
2
DD
C interface are dictated by a microcon-
2
C bus to check the incoming address
2
pin which can be set independent to
C interface is shown in Figure 2. The
3D
2
will increase the 3D effect. The
C interface operates at a voltage
2
C chip addresses are of the
2
DD
1
C standard is 400kHz. In
= 0, if ADR is logic low;
. This is ideal whenever
2
C interface is used to
2
CV
3D
DD
resistor. De-
)
2
C
18
C
Increasing the value of C
quency at which the 3D effect starts to occur, as shown by
Equation 1.
Activating the 3D effect will cause an increase in gain by a
multiplication factor of (1 + 20kΩ/R
will result in a gain increase by a multiplication factor of (1
+20kΩ/20kΩ) = 2 or 6dB whenever the 3D effect is activated.
The volume control can be programmed through the I
patible interface to compensate for the extra 6dB increase in
gain. For example, if the stereo volume control is set at 0dB
(11011 from Table 4) before the 3D effect is activated, the
volume control should be programmed to –6dB (10111 from
Table 4) immediately after the 3D effect has been activated.
Setting R
produce a pronounced 3D effect with a minimal increase in
output noise.
OUTPUT CAPACITOR-LESS (OCL) OPERATION AND
LAYOUT TECHNIQUES FOR OPTIMUM CROSSTALK
The LM4844’s OCL headphone architecture eliminates out-
put coupling capacitors. Unless the headphone is in shut-
down, the OCL output will be at a bias voltage of ½V
is applied to the stereo headphone jack’s sleeve. This voltage
matches the bias voltage present on LHP and RHP outputs
that drive the headphones. The headphones operate in a
manner similar to a bridge-tied load (BTL). Because the same
DC voltage is applied to both headphone speaker terminals
there is no net DC current flow through the speaker. AC cur-
rent flows through a headphone speaker as an audio signal’s
output amplitude increases on the speaker’s terminal.
The headphone jack’s sleeve is not connected to circuit
ground when used in OCL mode. Using the headphone output
jack as a line-level output will place the LM4844’s ½V
voltage on a plug’s sleeve connection.
Since the LHP and RHP outputs of the LM4844 share the OCL
output as a reference, certain layout techniques should be
used in order to achieve optimum crosstalk performance. The
crosstalk will depend on the parasitic resistance of the trace
connecting the LM4844 OCL output to the headphone jack
sleeve and on the load resistance value. Since the load re-
sistance is often predetermined, it is advisable to use a trace
that is as short and as wide as possible. Reasonable appli-
cation of this layout technique will result in crosstalk values of
60dB, as specified in the electrical characteristics table.
BRIDGE CONFIGURATION EXPLANATION
The LM4844 consists of two sets of bridged-tied amplifier
pairs that drive the left loudspeaker (LLS) and the right loud-
speaker (RLS). For this discussion, only the LLS bridge-tied
amplifier pair will be referred to. The LM4844 drives a load,
such as a speaker, connected between outputs, LLS+ and
LLS-. In the LLS amplifier block, the output of the amplifier
that drives LLS- serves as the input to the unity gain inverting
amplifier that drives LLS+.
This results in both amplifiers producing signals identical in
magnitude, but 180° out of phase. Taking advantage of this
phase difference, a load is placed between LLS- and LLS+
and driven differentially (commonly referred to as 'bridge
mode'). This results in a differential or BTL gain of:
3D
capacitor sets the low cutoff frequency of the 3D effect.
3D
= 20kΩ and C
f
3D(-3dB)
A
VD
= 1 / 2π(R
= 2(R
3D
3D
f
will decrease the low cutoff fre-
/ R
= 0.22μF allows the LM4844 to
i
) = 2
3D
)(C
3D
3D
). Setting R
)
3D
DD
to 20kΩ
2
C com-
DD
, which
bias
(1)
(2)