LM5072EVAL National Semiconductor, LM5072EVAL Datasheet - Page 21

• Manufacturer Part Number: LM5072EVAL
• Description: BOARD EVALUATION LM5072
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM5072EVAL

• Main Purpose: Special Purpose DC/DC, Power Over Ethernet
• Outputs And Type: 1, Isolated
• Power - Output: 9.9W
• Voltage - Output: 3.3V
• Current - Output: 3A
• Voltage - Input: 38 ~ 60V
• Regulator Topology: Flyback
• Frequency - Switching: 250kHz
• Board Type: Fully Populated
• Utilized Ic / Part: LM5072
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5.
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Consider the following when starting the PCB design:
1.
2.
3.
4.
5.
Also consider the following during PCB layout and routing.
1.
This re-configuration should make use of the spare pins
of the transformer.
R24 should be deleted from the schematic completely,
being replaced by a short connection for an isolated
application, or by an open for a non-isolated application.
Jumpers P5 and P6 (Figure 20) should be deleted from
the schematic completely, being replaced by a short
connection for an isolated application, or by an open for
a non-isolated application.
When the output is non-isolated, delete C20, C22, C25,
R7, R11, R16, R17, R24, U2, and U3. Replace C28 with
a short connection, and replace P5 and P6 with short
connections.
One may also modify the number of input and output
capacitors to achieve a more optimized design.
Try to use both sides of the PCB for part placement to
facilitate both layout and routing.
Place the power components in a pattern that minimizes
the lengths of the high current paths on the PCB.
Place the LM5072 and its critical peripheral parts closely.
Bypass capacitors and transient protection elements
should be near the LM5072.
Route the critical traces first, including both power and
signal traces. Make the length of the trace as short as
possible, and avoid excessive use of via holes.
Pay attention to grounding issues. Each reference
ground should be a copper plane or island. Use via holes
if necessary for direct connections of devices to their
appropriate return ground plane or island. Identify the
following ground returns:
R29, C3, P4, J3-pins 2 and 3, U1-pin 8, C28, and C29
are all returned to the COM ground plane.
C19, T1-pin 2, C23, U2-pin 3, R24, C26, C21, and U1-
pin 16 are all returned to this island, and the island should
be single point connected to the COM ground plane.
through C10, C12 through C17, C28, Z4, J5, and J7 are
all returned to the IGND ground plane.
island: R18, U3 and C20 are all returned to this island,
and the island should be single point connected to the
IGND ground plane.
Place the following power components in each group as
close as possible:
R14/R15. The high frequency switching current (pulse
current) flows through these parts in a loop. The physical
area enclosed by the loop should be as small as possible.
for the main output. The high frequency switching current
for the main output rail flows through these parts in a loop.
Primary power return COM: C4, C5, C6, R14, R15,
Primary control signal return, a ground return island:
Secondary power return IGND: T1-pins 6 and 7, C7
Secondary control signal return, a ground return
C4, C5 (if used), the primary winding of T1, Q1, and
D5, C7 through C10, and the secondary winding of T1
21
2.
3.
4.
5.
6.
7.
8.
9.
10. R9 should be directly routed from R14/R15.
11. D6 and Z1 should be placed to achieve the shortest
12. C2 and R4 should be placed to achieve the shortest
13. Q1, D5, D8, and U1 (LM5072) should be installed on
14. Avoid spiral trace pattern.
15. Avoid placing switching traces near any traces in the
16. Pay attention to trace width. Try to make the power traces
After the first placement and routing is completed, make nec-
essary modifications to optimize the design.
The physical area enclosed by the loop should be as
small as possible.
the second output, if used. The high frequency switching
current for the second output rail flows through these
parts in a loop. The physical area enclosed by the loop
should be as small as possible.
also be as close as possible to the capacitor bank
consisting of C7 through C10 in order to minimize the
conduction losses on the PCB. Ceramic capacitor C15
should be placed directly at the output port.
second output rail. L2 should also be as close as possible
to C12 and C13 in order to minimize the conduction
losses on the PCB. Ceramic capacitor C14 should be
directly placed at the output port
U1 (LM5072) should be placed close to Q1 in the
orientation such that the gate drive output pin (OUT, Pin
9) is close to Q1’s gate.
(iii) Z2 and C27 must be placed directly across the VIN
and VEE pins for best protection against input transients.
In a rear auxiliary application, C27 should be removed
and C29 should be installed very close to the RTN and
VEE pins.
C19 should be placed directly across the VCC and ARTN
pins.
C23 should be placed directly across the CS and ARTN
pins.
R21 should be placed directly across the RT and ARTN
pins.
C26 should be placed directly across the SS and ARTN
pins.
C21 should be placed directly across the nPGOOD and
ARTN pins.
R25 should be directly routed from the output port.
connection from C4 or C5 to the drain pad(s) of Q1 for
better snubbing.
connection across D5.
thermal pads having adequate thermal vias down
through all PCB Layers and an exposed thermal pad on
the other side of the PCB.
regulator feedback loop.
as wide as possible. Conversely, do not make signal
traces wider than needed.
D8, C12 and C13, and the secondary winding of T1 for
L3, C15, C16, J4 and J5 (if posts are used). L3 should
L2, C14, C17, Z4, J6 and J7 (if posts are used) for the
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