DK86064-2 Fujitsu Semiconductor America Inc, DK86064-2 Datasheet - Page 23

KIT DEB DUAL 14BIT DAC MB86064

DK86064-2

Manufacturer Part Number
DK86064-2
Description
KIT DEB DUAL 14BIT DAC MB86064
Manufacturer
Fujitsu Semiconductor America Inc
Datasheets

Specifications of DK86064-2

Number Of Dac's
2
Number Of Bits
14
Outputs And Type
1, Differential
Sampling Rate (per Second)
1G
Data Interface
Serial
Dac Type
Current
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
MB86064
For Use With
865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
865-1010
October 2005 Version 1.2
FME/MS/DAC80/DS/4972
MB86064 Dual 14-bit 1GSa/s DAC
3.2
To make full use of the Waveform Memory Module user waveforms may be downloaded to the on-
chip memories. Different waveforms of equal length may be stored in each RAM, totalling up to 16k
points (in multiples of eight points). Configuration of the WMM [EVEN/ODD] MUX CTRL registers will
determine which vector is routed to which DAC.
Copyright © 2004-2005 Fujitsu Microelectronics Europe GmbH
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
ODD] CONFIG
WMM [EVEN/
Waveform Memory Module
Table 16: WMM Register: WMM [EVEN/ODD] CONFIG [0x10/0x20] (Part 1 of 2)
Waveform Memory Module Operation
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
(bit)
Before the waveform memories can be used they must be enabled through register WMM
[EVEN/ODD] CONFIG, bit ram_ih. See Table 16.
mux_a_ctrl[2]
mux_a_ctrl[2]
1
mux_a_ctrl[3]
Figure 15 Waveform Memories Routing Diagram
Controller
Controller
Access
Access
RAM
RAM
Label
ram_ih
RAM A
RAM A
Waveform Memory inhibit control
0 = Memories Enabled
1 = Memories Disabled (default)
EVEN
ODD
RAM B
RAM B
EVEN
ODD
Function
Production
Controller
Controller
Access
Access
RAM
RAM
mux_b_ctrl[3]
mux_b_ctrl[2]
mux_b_ctrl[2]
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