EVAL-AD5379EBZ Analog Devices Inc, EVAL-AD5379EBZ Datasheet - Page 23

• Manufacturer Part Number: EVAL-AD5379EBZ
• Description: BOARD EVALUATION FOR AD5379
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5379EBZ

• Number Of Dac's: 40
• Number Of Bits: 14
• Outputs And Type: 40, Single Ended
• Sampling Rate (per Second): 50k
• Data Interface: Serial, Parallel
• Settling Time: 20µs
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5379
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Daisy-Chain Mode
For systems that contain several DACs, the SDO pin can be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines.
Connecting the DCEN (daisy-chain enable) pin high enables
daisy-chain mode. The first falling edge of SYNC starts the
write cycle. The SCLK is continuously applied to the input shift
register when SYNC is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting this line to
the DIN input on the next device in the chain, a multidevice
interface is constructed. For each AD5379 in the system,
24 clock pulses are required. Therefore, the total number of
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clock cycles must equal 24N, where N is the total number of
AD5379 devices in the chain. If fewer than 24 clocks are
applied, the write sequence is ignored.
When the serial transfer to all devices has been completed,
SYNC is taken high. This latches the input data in each device
in the daisy chain and prevents any additional data from being
clocked into the input shift register.
A continuous SCLK source can be used if SYNC is held low for
the correct number of clock cycles. Alternatively, a burst clock
containing the exact number of clock cycles can be used and
SYNC taken high after the final clock to latch the data.
When the transfer to all input registers is complete, a common
LDAC signal updates all DAC registers, and all analog outputs
are simultaneously updated.
AD5379