AD9742ACP-PCB Analog Devices Inc, AD9742ACP-PCB Datasheet
AD9742ACP-PCB
Specifications of AD9742ACP-PCB
Related parts for AD9742ACP-PCB
AD9742ACP-PCB Summary of contents
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FEATURES High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SNR @ 5 MHz output, 125 MSPS Twos complement or straight binary data format Differential current outputs Power dissipation: ...
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AD9742 TABLE OF CONTENTS Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 Dynamic Specifications ............................................................... 4 Digital Specifications ................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 8 Typical Performance ...
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SPECIFICATIONS DC SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3 MIN MAX Table 1. Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error ...
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AD9742 DYNAMIC SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3 MIN MAX minated, unless otherwise noted. Table 2 Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) CLOCK 1 Output ...
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Parameter Multitone Power Ratio (8 Tones at 400 kHz Spacing MSPS 15.0 MHz to 18.2 MHz CLOCK OUT 0 dBFS Output −6 dBFS Output −12 dBFS Output −18 dBFS Output 1 Measured single-ended into 50 ...
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AD9742 ABSOLUTE MAXIMUM RATINGS Table 4. With Parameter Respect to Min AVDD ACOM −0.3 DVDD DCOM −0.3 CLKVDD CLKCOM −0.3 ACOM DCOM −0.3 ACOM CLKCOM −0.3 DCOM CLKCOM −0.3 AVDD DVDD −3.9 AVDD CLKVDD −3.9 DVDD CLKVDD −3.9 CLOCK, SLEEP ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS (MSB) DB11 1 28 DB10 2 27 DB9 3 26 DB8 4 25 DB7 5 24 AD9742 DB6 6 23 TOP VIEW DB5 7 22 (Not to Scale) DB4 8 21 DB3 9 20 DB2 ...
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AD9742 TERMINOLOGY Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the ac- tual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential ...
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TYPICAL PERFORMANCE CHARACTERISTICS 95 125MSPS 90 210MSPS (LFCSP 65MSPS 75 210MSPS 70 165MSPS 65 125MSPS (LFCSP (MHz) OUT Figure 6. SFDR vs dBFS OUT ...
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AD9742 65MSPS 80 125MSPS 75 165MSPS 210MSPS (LFCSP –25 –20 –15 –10 A (dBFS) OUT Figure 12. Single-Tone SFDR vs. A OUT 125MSPS (LFCSP) 65MSPS 80 75 165MSPS ...
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TEMPERATURE (°C) Figure 18. SFDR vs. Temperature @ 165 MSPS, 0 dBFS 78MSPS CLOCK – 15.0MHz OUT SFDR ...
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AD9742 FUNCTIONAL DESCRIPTION Figure 22 shows a simplified block diagram of the AD9742. The AD9742 consists of a DAC, digital control logic, and full-scale output current control. The DAC contains a PMOS current source array capable of providing up to ...
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REFERENCE CONTROL AMPLIFIER The AD9742 contains a control amplifier that is used to regulate the full-scale output current The control amplifier is OUTFS configured as a V-I converter, as shown in Figure 24, so that its current output, ...
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AD9742 Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). Since the output currents of IOUTA and IOUTB are complementary, they become additive when ...
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The final clock mode allows for a reduced external component count when the DAC clock is distributed on the board using PECL logic. The internal termination configuration is shown in Figure 26. These termination resistors are untrimmed and can vary ...
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AD9742 12 10 DIFF 8 PECL 100 150 f (MSPS) CLOCK Figure 30. I vs. f and Clock Mode CLKVDD CLOCK APPLYING THE AD9742 Output Configurations The following sections illustrate some typical output ...
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The differential circuit shown in Figure 33 provides the necessary level shifting required in a single-supply system. In this case, AVDD, which is the positive analog supply for both the AD9742 and the op amp, is also used to level ...
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AD9742 FREQUENCY (MHz) Figure 36. Power Supply Rejection Ratio (PSRR) Note that the ratio in Figure 36 is calculated as amps out/volts in. Noise on the ...
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EVALUATION BOARD GENERAL DESCRIPTION The TxDAC family evaluation boards allow for easy setup and testing of any TxDAC product in the SOIC and LFCSP pack- ages. Careful attention to layout and circuit design, combined with a prototyping area, allows the ...
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AD9742 AVDD + C14 C16 C17 10µF 0.1µF 0.1µF 16V DVDD + C15 C18 C19 10µF 0.1µF 0.1µF 16V CKEXT JP4 28 1 DB13 CLOCK DB13 2 27 DB12 DVDD DB12 3 26 DB11 DCOM DB11 4 25 DB10 MODE ...
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Figure 40. SOIC Evaluation Board—Primary Side Figure 41. SOIC Evaluation Board—Secondary Side Rev Page AD9742 ...
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AD9742 Figure 42. SOIC Evaluation Board—Ground Plane Figure 43. SOIC Evaluation Board—Power Plane Rev Page ...
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Figure 44. SOIC Evaluation Board Assembly—Primary Side Figure 45. SOIC Evaluation Board Assembly—Secondary Side Rev Page AD9742 ...
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AD9742 L1 BEAD TB1 1 BLK C3 0.1µF TP2 TB1 2 L2 BEAD TB3 1 BLK C7 0.1µF TP4 TB3 2 L3 BEAD TB4 1 BLK C9 0.1µF TP6 TB4 100Ω 100Ω DB13X DB12X DB11X DB10X DB9X ...
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DB7 DB8 DB7 2 31 DB6 DB9 DB6 30 3 DVDD DB10 DVDD 4 29 DB5 DB11 DB5 5 28 DB4 DB12 DB4 27 6 DB3 DB13 DB3 7 26 DB2 DCOM1 DB2 25 8 DB1 SLEEP DB1 ...
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AD9742 Figure 49. LFCSP Evaluation Board Layout—Primary Side Figure 50. LFCSP Evaluation Board Layout—Secondary Side Rev Page ...
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Figure 51. LFCSP Evaluation Board Layout—Ground Plane Figure 52. LFCSP Evaluation Board Layout—Power Plane Rev Page AD9742 ...
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AD9742 Figure 53. LFCSP Evaluation Board Layout Assembly—Primary Side Figure 54. LFCSP Evaluation Board Layout Assembly—Secondary Side Rev Page ...
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OUTLINE DIMENSIONS PIN 1 0.15 0.05 COPLANARITY 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 9.80 9.70 9. 4.50 4.40 4. 0.65 BSC 1.20 MAX 0.30 0.20 0.19 SEATING 0.09 PLANE 0.10 COMPLIANT TO JEDEC ...
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... AD9742ACPRL7 −40°C to +85°C 2 AD9742ACPZ −40°C to +85°C AD9742ACPZRL7 2 −40°C to +85°C AD9742-EB AD9742ACP-PCB Small Outline IC Thin Shrink Small Outline Package Lead Frame Chip Scale Package Pb-free part. 5.00 BSC SQ 0.60 MAX 24 PIN 1 INDICATOR ...
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NOTES Rev Page AD9742 ...
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AD9742 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective owners. C02912–0–6/04(B) Rev Page ...