EVAL-AD7655CB Analog Devices Inc, EVAL-AD7655CB Datasheet - Page 22

• Manufacturer Part Number: EVAL-AD7655CB
• Description: BOARD EVAL FOR AD7655
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7655CB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 1M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 4 Single Ended
• Input Range: 0 ~ 2 V
• Power (typ) @ Conditions: 120mW @ 1MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7655
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7655
SLAVE SERIAL INTERFACE
External Clock
The AD7655 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/ INT pin is
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS . When both CS
and RD are low, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 31 and Figure 32 show the detailed timing
diagrams of these methods.
While the AD7655 is performing a bit decision, it is important
that voltage transients do not occur on digital input/output pins
or degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase of each channel, because the AD7655 provides error
correction circuitry that can correct for an improper bit
decision made during the first half of the conversion phase. For
this reason, it is recommended that when an external clock is
provided, it is a discontinuous clock that is toggling only when
BUSY is low or, more importantly, that it does not transition
during the latter half of EOC high.
External Discontinuous Clock Data Read After Convert
Although the maximum throughput cannot be achieved in this
mode, it is the most recommended of the serial slave modes.
Figure 31 shows the detailed timing diagrams of this mode.
After a conversion is complete, indicated by BUSY returning
low, the conversion results can be read while both CS and RD
are low. Data is shifted out from both channels’ MSB first, with
32 clock pulses, and is valid on both rising and falling edges of
the clock.
Among the advantages of using this mode is that conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 40 MHz, which accommodates both slow digital host
interface and the fastest serial reading.
Finally, in this mode only, the AD7655 provides a daisy-chain
feature using the RDC/SDIN (serial data in) input pin for
cascading multiple converters together. This feature is useful for
reducing component count and wiring connections when it is
desired, as in isolated multiconverter applications.
Rev. B | Page 22 of 28
An example of the concatenation of two devices is shown in
Figure 30. Simultaneous sampling is possible by using a
common CNVST signal. Note that the RDC/SDIN input is
latched on the edge of SCLK opposite the one used to shift out
the data on SDOUT. Therefore, the MSB of the upstream
converter follows the LSB of the downstream converter on the
next SCLK cycle. The SDIN input should be tied either high or
low on the most upstream converter in the chain.
External Clock Data Read (Previous) During Convert
Figure 32 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 32 clock pulses, and is valid on both the rising
and falling edges of the clock. The 32 bits have to be read before
the current conversion is completed; otherwise, RDERROR is
pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain
feature in this mode, and RDC/SDIN input should always be
tied either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock (at least 32 MHz in impulse mode and
40 MHz in normal mode) is recommended to ensure that all of
the bits are read during the first half of each conversion phase
( EOC high, t
It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion has been
initiated. This allows the use of a slower clock speed such as
26 MHz in impulse mode and 30 MHz in normal mode.
CNVST IN
SCLK IN
CS IN
RDC/SDIN
Figure 30. Two AD7655s in a Daisy-Chain Configuration
#2 (UPSTREAM)
AD7655
11
BUSY
, t
12
).
SDOUT
CNVST
SCLK
CS
RDC/SDIN
#1 (DOWNSTREAM)
AD7655
BUSY
SDOUT
CNVST
SCLK
CS
BUSY
OUT
DATA
OUT