EVAL-ADUC824QS Analog Devices Inc, EVAL-ADUC824QS Datasheet - Page 15

KIT DEV FOR ADUC824 QUICK START

EVAL-ADUC824QS

Manufacturer Part Number
EVAL-ADUC824QS
Description
KIT DEV FOR ADUC824 QUICK START
Manufacturer
Analog Devices Inc
Series
QuickStart™ Kitr
Type
8052-corer
Datasheet

Specifications of EVAL-ADUC824QS

Contents
Evaluation Board, Power Supply, Cable, Software and Documentation
For Use With/related Products
ADuC824
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Parameter
SPI MASTER MODE TIMING (CPHA = 0)
Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.57 MHz and
b. SPI bit-rate selection bits SPR1 and SPR0 bits in SPICON SFR set to 0 and 0 respectively.
t
t
t
t
t
t
t
t
t
t
SL
SH
DAV
DOSU
DSU
DHD
DF
DR
SR
SF
SCLOCK Low Pulsewidth
SCLOCK High Pulsewidth
Data Output Valid after SCLOCK Edge
Data Output Setup before SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
(CPOL = 0)
(CPOL = 1)
SCLOCK
SCLOCK
MOSI
MISO
t
DOSU
t
DSU
MSB IN
MSB
t
DHD
t
SH
t
DF
t
DAV
t
SL
t
DR
BITS 6–1
BITS 6–1
Min
100
100
Typ
630
630
10
10
10
10
LSB IN
t
SR
LSB
Max
50
150
25
25
25
25
t
SF
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADuC824
Figure
9
9
9
9
9
9
9
9
9
9

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