EVAL-AD7679CB Analog Devices Inc, EVAL-AD7679CB Datasheet
EVAL-AD7679CB
Specifications of EVAL-AD7679CB
Related parts for EVAL-AD7679CB
EVAL-AD7679CB Summary of contents
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FEATURES 18-bit resolution with no missing codes No pipeline delay (SAR architecture) Differential input range: ± REF REF Throughput: 570 kSPS INL: ±2.5 LSB max (±9.5 ppm of full scale) Dynamic range : 103 dB ...
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... Rev. A Changes to Zero Error Parameter ........................... 3 MIN MAX Changes to Endnote 3 ...................................................................... 4 Changes to Pin Configuration Section .......................................... 8 Changes to Evaluating the AD7679’s Performance Section ...... 25 Changes to Ordering Guide .......................................................... 26 7/03—Revision 0: Initial Version Typical Connection Diagram ................................................... 17 Power Dissipation versus Throughput .................................... 19 Conversion Control ................................................................... 19 Digital Interface .......................................................................... 20 Parallel Interface ......................................................................... 20 Serial Interface ...
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SPECIFICATIONS –40°C to +85° 4.096 V, AVDD = DVDD OVDD = 2 5.25 V, unless otherwise noted. REF Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current ...
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AD7679 Parameter DIGITAL INPUTS Logic Levels DIGITAL OUTPUTS 5 Data Format Pipeline Delay POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current AVDD 8 DVDD 8 OVDD ...
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TIMING SPECIFICATIONS –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2 5.25 V, unless otherwise noted. Table 3. Parameter Refer to Figure 32 and Figure 33 Convert Pulsewidth Time between Conversions CNVST LOW to BUSY ...
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AD7679 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time ...
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ABSOLUTE MAXIMUM RATINGS Table 5.AD7679 Absolute Maximum Ratings Parameter Analog Inputs 2 2 IN+ , IN– , REF, REFBUFIN, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD, OVDD AVDD to DVDD, AVDD to OVDD DVDD ...
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AD7679 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D4/DIVSCLK[0] D5/DIVSCLK[1] NOTES CONNECT. 2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO AGND. THIS CONNECTION Table 6. Pin Function Descriptions Pin No. Mnemonic Type 1 Description 1, 44 AGND P ...
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Pin No. Mnemonic Type Description 13 D6 DI/O In all modes except MODE = 3, this output is used as Bit 6 of the parallel port data output bus. or EXT/INT When MODE = 3 (serial mode), this input, ...
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AD7679 1 Pin No. Mnemonic Type Description Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Start Conversion. If CNVST is ...
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DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before ...
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AD7679 TYPICAL PERFORMANCE CHARACTERISTICS 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 0 65536 131072 CODE Figure 5. Integral Nonlinearity vs. Code 70000 58510 59001 60000 50000 40000 30000 20000 7584 10000 1FEBD ...
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POSITIVE DNL (LSB) Figure 11. Typical Positive DNL Distribution (424 Units) 180 160 140 120 100 –1.00 –0.75 –0.50 –0.25 NEGATIVE DNL (LSB) Figure ...
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AD7679 100 SNR 99 S/(N+ –55 –35 – TEMPERATURE (°C) Figure 17. SNR, S/(N+D), and ENOB vs. Temperature –100 THD –110 THIRD HARMONIC –120 SECOND HARMONIC –130 –140 –55 –35 – ...
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CIRCUIT INFORMATION IN+ REF REFGND IN– The AD7679 is a very fast, low power, single-supply, precise 18-bit analog-to-digital converter (ADC) using successive approximation architecture. The AD7679’s linearity and dynamic range are similar or better than many Σ-Δ ADCs. With the ...
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AD7679 Transfer Functions Except in 18-bit interface mode, the AD7679 offers straight binary and twos complement output coding when using OB See Figure 24 and Table 8 for the ideal transfer characteristic. 111...111 111...110 111...101 000...010 000...001 000...000 ...
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TYPICAL CONNECTION DIAGRAM Figure 25 shows a typical connection diagram for the AD7679. Different circuitry shown on this diagram is optional and is discussed later in this data sheet. Analog Inputs Figure 26 shows a simplified analog input section of ...
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AD7679 The SNR degradation due to the amplifier is ⎛ ⎜ ⎜ = SNR 20 log ⎜ LOSS ⎜ + π ⎜ 625 ⎝ where the –3 dB input bandwidth in MHz of the AD7679 –3dB (26 MHz) ...
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Power Supply The AD7679 uses three sets of power supply pins: an analog 5 V supply (AVDD), a digital 5 V core supply (DVDD), and a digital output interface supply (OVDD). The OVDD supply defines the output logic level and ...
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AD7679 DIGITAL INTERFACE The AD7679 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The AD7679 digital interface ...
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MASTER SERIAL INTERFACE Internal Clock The AD7679 is configured to generate and provide the serial data clock SCLK when the EXT/ INT pin is held low. The AD7679 also generates a SYNC signal to indicate to the host when the ...
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AD7679 EXT/INT = 0 CS, RD CNVST BUSY t 17 SYNC SCLK t X SDOUT Figure 39. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) SLAVE SERIAL INTERFACE External ...
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EXT/INT = 1 CS BUSY SCLK SDOUT X D17 D16 SDIN X17 X16 t 33 Figure 40. Slave Serial Data Timing for Reading ...
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AD7679 BUSY AD7679 #2 (UPSTREAM) #1 (DOWNSTREAM) RDC/SDIN SDOUT RDC/SDIN CNVST CS SCLK SCLK CNVST IN Figure 42. Two AD7679s in a Daisy-Chain Configuration External Clock Data Read during Conversion Figure 41 shows the detailed timing diagrams ...
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... An evaluation board for the AD7679 allows a quick means to measure both dc (histograms and time domain) and ac (time and frequency domain) performances of the converter. The EVAL-AD7679CBZ is an evaluation board package that includes a fully assembled and tested evaluation board, documentation, and software. The accompanying software ...
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... SEATING PLANE ORDERING GUIDE Model 1 AD7679ASTZ 1 AD7679ASTZRL 1 AD7679ACPZ 1 AD7679ACPZRL EVAL-AD7679CBZ EVAL-CONTROL BRD2Z EVAL-CONTROL BRD3Z 1 EVAL-CED1Z RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 3 These capture boards allow control and communicate with all Analog Devices evaluation boards ending in ED for EVAL-CED1Z and CB for EVAL-CONTROL BRDxZ ( ...
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NOTES Rev Page AD7679 ...
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AD7679 NOTES ©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03085-0-6/09(A) Rev Page ...