AD9956-VCO/PCB Analog Devices Inc, AD9956-VCO/PCB Datasheet - Page 28

• Manufacturer Part Number: AD9956-VCO/PCB
• Description: BOARD EVAL 14BIT 1.8V 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9956-VCO/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD9956
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9956
CFR1 <17> Linear Sweep Enable
This bit turns on the frequency accumulator, which enables the
DDS to perform linear sweeping.
CFR1<17> = 0 (default). The DDS generates frequencies in
single-tone mode.
CFR1<17> = 1. The DDS uses the frequency accumulator to
sweep the frequency tuning word being sent to the phase
accumulator according to the values set in the delta frequency
tuning word and delta frequency ramp rate registers. For a
detailed explanation of this mode, see the linear sweep mode of
operation section.
CFR1 <16> Linear Sweep No Dwell
This bit dictates the behavior of the DDS core upon completion
of a linear sweep.
CFR1<16> = 0 (default). Upon reaching the upper value of the
sweep (FTW1), the DDS holds at the frequency value stored in
FTW1.
CFR1<16> = 1. Upon reaching the upper value of the sweep
(FTW1), the DDS returns to the initial value in the sweep
(FTW0) and continues to output that frequency until a new
sweep is initiated (by bringing PS0 low and then high).
CFR1 <15> LSB First Serial Data Mode
The serial data transfer to the device can be either MSB first or
LSB first. This bit controls that operation.
CFR1<15> = 0 (default). Serial data transfer to the device is in
MSB first mode.
CFR1<15> = 1. Serial data transfer to the device is in LSB first
mode.
CFR1<14> SDI/O Input Only (3-Wire Serial Data Mode)
The serial port on the AD9956 can act in 2-wire mode (SCLK
and SDI/O) or 3-wire mode (SCLK, SDI/O, and SDO). This bit
toggles the serial port between these two modes.
CFR1<14> = 0 (default). Serial data transfer to the device is in
2-wire mode. The SDI/O pin is bidirectional.
CFR1<14> = 1. Serial data transfer to the device is in 3-wire
mode. The SDI/O pin is input only.
CFR1<13:8> Open
Unused locations. Write a Logic 0.
Rev. A | Page 28 of 32
CFR1<7> Digital Power-Down
This bit powers down the digital circuitry not directly related to
the I/O port. The I/O port functionality is not suspended, re-
gardless of the state of this bit.
CFR1<7> = 0 (default). Digital logic operating as normal.
CFR1<7> = 1. All digital logic not directly related to the I/O
port is powered down. Internal digital clocks are suspended.
CFR1<6> Phase Frequency Detector Input Power-Down
This bit controls the input buffers on the phase frequency detec-
tor. It provides a way to gate external signals from the phase
frequency detector itself.
CFR1<6> = 0 (default). Phase frequency detector input buffers
are functioning normally.
CFR1<6> = 1. Phase frequency detector input buffers are pow-
ered down, isolating the phase frequency detector from the
outside world.
CFR1<5> PLLREF Crystal Enable
The AD9956 phase frequency detector has an on-chip oscillator
circuit. When enabled, the reference input to the phase fre-
quency detector (PLLREF/ PLLREF
CFR1<5> = 0 (default). Phase frequency detector reference
input operates as a standard analog input.
CFR1<5> = 1. Reference input oscillator circuit is enabled,
allowing the use of a crystal for the reference of the phase
frequency detector.
CFR1<4> SYNC_CLK Disable
If synchronization of multiple devices is not required, the spec-
tral energy resulting from this signal can be reduced by gating
the output buffer off. This function gates the internal clock ref-
erence SYNC_CLK (SYSCLK/4) off of the SYNC_OUT pin.
CFR1<4> = 0 (default). SYNC_CLK signal is present on the
SYNC_OUT pin and is ready to be ported to other devices.
CFR1<4> = 1. SYNC_CLK signal is gated off, putting the
SYNC_OUT pin into a high impedance state.
CFR1<3> Automatic Synchronization
One of the synchronization modes of the AD9956 forces the
DDS core to derive the internal reference from an external ref-
erence supplied on the SYNC_IN pin. For details on synchroni-
zation modes for the DDS core, see the Synchronization Modes
for Multiple Devices section.
) can be driven by a crystal.