AD9880/PCB Analog Devices Inc, AD9880/PCB Datasheet - Page 41

• Manufacturer Part Number: AD9880/PCB
• Description: BOARD EVALUATION PCB AD9880
• Manufacturer: Analog Devices Inc

Specifications of AD9880/PCB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

0x15
Table 21. Coast Detection Results
Detect
0
1
POLARITY STATUS
0x16
Table 22. Detected Hsync0 Polarity Results
Detect
0
1
0x16
Table 23. Detected Hsync1 Polarity Result
Detect
0
1
0x16
Table 24. Detected Vsync0 Polarity Results
Detect
0
1
0x16
Table 25. Detected Vsync 1 Polarity Results
Detect
0
1
0x16
Table 26. Detected Coast Polarity Results
Detect
0
1
0x16
0x16
1
This bit detects activity on the EXTCLK/EXTCOAST
pin. It indicates that one of the two signals is active,
but it doesn’t indicate if it is EXTCLK or EXTCOAST.
A dc signal is not detected.
7
Indicates the polarity of the Hsync0 input.
6
Indicates the polarity of the Hsync1 input.
5
Indicates the polarity of the Vsync0 input.
4
Indicates the polarity of the Vsync1 input.
3 Coast Polarity
Indicates the polarity of the external Coast signal.
2
1
Indicates whether sync filter is locked to periodic sync
signals. 0 = sync filter locked to periodic sync signal.
1 = sync filter not locked.
Result
Coast polarity negative
Coast polarity positive
Result
Hsync polarity negative
Hsync polarity positive
Result
Hsync polarity negative
Hsync polarity positive
Result
Vsync polarity negative
Vsync polarity Positive
Result
Vsync polarity negative
Vsync polarity positive
Coast Detection Bit
Hsync0 Polarity
Hsync 1 Polarity
Vsync0 Polarity
Vsync1 Polarity
Pseudo Sync Detected
Sync Filter Locked
Result
No activity detected
Activity detected
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Table 27. Sync Filter Lock Detect
Detect
0
1
0x16
0x17
0x18
0x19
0x1A
0x1B
Table 28. Red Clamp
Select
0
1
0x1B
Table 29. Green Clamp
Select
0
1
Result
Channel clamped to ground during clamping period
Channel clamped to midscale during clamping period
Result
Channel clamped to ground during clamping period
Channel clamped to midscale during clamping period
0
3-0
The 4 MSBs of the 12-bit counter that reports the
number of Hsyncs/Vsync on the active input. This is
useful in determining the mode and an aid in setting
the PLL divide ratio.
7-0
The 8 LSBs of the 12-bit counter that reports the
number of Hsyncs/Vsync on the active input.
7-0
Number of pixel clocks after trailing edge of Hsync to
begin clamp. The power-up default is 8.
7-0
Number of pixel clocks to clamp. The power-up
default is 0x14.
7
This bit selects whether the red channel is clamped to
ground or midscale. Ground clamping is used for red
in RGB applications and midscale clamping is used in
YPrPb (YUV) applications.
The power-up default is 0.
6
This bit selects whether the green channel is clamped
to ground or midscale. Ground clamping is normally
used for green in RGB applications and YPrPb (YUV)
applications.
The power-up default is 0.
Sync filter locked to periodic sync signal
Sync filter not locked to periodic sync signal
Result
Bad Sync Detect
Hsyncs per Vsync MSBs
Hsyncs per Vsync LSBs
Clamp Placement
Clamp Duration
Red Clamp Select
Green Clamp Select
AD9880