AD9880/PCB Analog Devices Inc, AD9880/PCB Datasheet - Page 48

• Manufacturer Part Number: AD9880/PCB
• Description: BOARD EVALUATION PCB AD9880
• Manufacturer: Analog Devices Inc

Specifications of AD9880/PCB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9880
Table 71. DVI Hsync Polarity Detect
Detect
0
1
0x30
Table 72. DVI Vsync Polarity Detect
Detect
0
1
0x30
Table 73.
Select
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
MACROVISION
0x31
0x31
0x32
0x32
4
This read-only bit indicates the polarity of the DVI
Vsync.
3-0
These read-only bits indicate the pixel repetition on
DVI. 0 = 1×, 1 = 2×, 2 = 3×, up to a maximum
repetition of 10× (0x9).
7-4
These bits set the pseudo sync pulse width maximum
for Macrovision detection in pixel clocks. This is
functional for 13.5 MHz SDTV or 27 MHz progressive
scan. Power up default is 9.
3-0
These bits set the pseudo sync pulse width maximum
for Macrovision detection in pixel clocks. This is
functional for 13.5 MHz SDTV or 27 MHz progressive
scan. Power up default is 6.
7
Tells the Macrovision detection engine whether we are
oversampling or not. This accommodates 27 MHz
sampling for SDTV and 54 MHz sampling for
progressive scan and is used as a correction factor for
clock counts. Power up default is 0.
6
Tells the Macrovision detection engine to enter PAL
mode when set to 1. Default is 0 for NTSC mode.
DVI Vsync Polarity
HDMI Pixel Repetition
Macrovision Pulse Max
Macrovision Pulse Min
Macrovision Oversample Enable
Macrovision PAL Enable
Result
DVI Hsync polarity is low active
DVI Hsync polarity is high active
Result
DVI Vsync polarity is low active
DVI Vsync polarity is high active
Repetition Multiplier
1×
2×
3×
4×
5×
6×
7×
8×
9×
10×
Rev. 0 | Page 48 of 64
0x32
0x33
0x33
0x33
0x34
0x34
0x34
0x34
0x34
5-0
Sets the start line for Macrovision detection. Along
with Register 0x33, Bits [5:0] they define the region
where MV pulses are expected to occur. The power-up
default is Line 13.
7
0 = standard definition
1 = progressive scan mode
6
This defines whether preset values are used for the
MV line counts and pulse widths or the values stored
in I
0 = use hard coded settings for line counts and pulse
widths
1 = use I
5-0
Sets the end line for Macrovision detection. Along
with Register 0x32, Bits [5:0] they define the region
where MV pulses are expected to occur. The power up
default is Line 21.
7-6
Sets the number of pulses required in the last three
lines (SD mode only). If there is not at least this
number of MV pulses, the engine stops. These two
bits define the following pulse counts:
00 = 6
01 = 4
10 = 5 (default)
11 = 7
5
Sets whether the audio PLL is in low frequency mode
or not. Low frequency mode should only be set for
pixel clocks < 80 MHz.
4
Allows the previous bit to be used to set low frequency
mode rather than the internal autodetect.
3
0 = repeat Cb/Cr values
1 = interpolate Cb/Cr values
2
Enables the FIR filter for 4:2:2 CbCr output.
2
C registers.
2
C values for these settings
Macrovision Line Count Start
Macrovision Line Count End
Low Frequency Override
Macrovision Detect Mode
Macrovision Settings Override
Macrovision Pulse Limit Select
Low Frequency Mode
Up Conversion Mode
CbCr Filter Enable