Z86E4000ZDV Zilog, Z86E4000ZDV Datasheet
Z86E4000ZDV
Specifications of Z86E4000ZDV
Related parts for Z86E4000ZDV
Z86E4000ZDV Summary of contents
Page 1
... Input/Output Lines Auto Latches Auto Power-On Reset (POR) GENERAL DESCRIPTION The Z86E30/E31/E40 8-Bit One-Time Programmable (OTP) Microcontrollers are members of Zilog's single-chip ® Z8 MCU family featuring enhanced wake-up circuitry, programmable Watch-Dog Timers, Low Noise EMI op- tions, and easy hardware/software system expansion ca- pability ...
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... Figure 1. Z86E30/E31/E40 Functional Block Diagram 2 Device XTAL GND CC Instruction Control ALU FLAGS Register Pointer Register File Port Address or I/O Address/Data or I/O (Nibble Programmable) (Byte Programmable Zilog (E40 Only R/W RESET Machine Timing & RESET WDT , POR OTP Program Counter Port 1 8 (E40 Only) DS97Z8X0502 ...
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... Zilog AD 11 MCU MSN Port Port 0 PGM + T est Mode Logic EPM PGM P32 P30 CE XT1 Figure 2. EPROM Programming Block Diagram DS97Z8X0502 11- 0 Address MUX EPROM TEST ROM OTP Options V PP P33 Z86E30/E31/E40 Z8 4K OTP Microcontroller Data MUX Port 2 OE P31 ...
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... Input Port 3, Pin 5 Output Port 3, Pin 7 Output Port 3, Pin 6 Output Port 3, Pin 0 Input Port 0, Pins 0,1 In/Output Port 1, Pins 0,1 In/Output Port 0, Pin 2 In/Output Ground Port 1, Pins 2,3 In/Output Port 0, Pin 3 In/Output Port 2, Pins 0,1,2,3,4 In/Output Data Strobe Output DS97Z8X0502 Zilog ...
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... Zilog Table 2. 44-Pin PLCC Pin Identification Pin # Symbol Function 1–2 GND Ground 3–4 P12–P13 Port 1, Pins 2,3 5 P03 Port 0, Pin 3 6–10 P20–P24 Port 2, Pins 0,1,2,3,4 In/Output 11 DS Data Strobe Connection 13 R/W Read/Write 14–16 P25–P27 Port 2, Pins 5,6,7 17– ...
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... Table 3. 44-Pin QFP Pin Identification Symbol Function P02 Port 0, Pin 2 Ground Port 1, Pins 2,3 P03 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 DS Data Strobe NC No Connection R/W Read/Write Port 2, Pins 5,6,7 P04 Port 0, Pin 4 DS97Z8X0502 Zilog Direction In/Output In/Output In/Output In/Output Output Output In/Output In/Output ...
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... Zilog 40-Pin DIP EPM Figure 6. 40-Pin DIP Pin Configuration EPROM Mode DS97Z8X0502 Table 4. 40-Pin DIP Package Pin Identification 40 NC Pin # Symbol 2–4 D5–D7 D1 5–7 A4–A6 D0 8– GND 12– EPM PGM 19 A8 A10 20–21 NC A11 A11 A10 25 PGM 26– ...
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... PGM A10 A11 EPM EPROM Programming Mode Symbol Function Direction V Prog. Voltage Input PP A8 Address 8 Input NC No Connection A9 Address 9 Input A11 Address 11 Input A10 Address 10 Input PGM Prog. Mode Input A0,A1 Address 0,1 Input NC No Connection A2 Address 2 Input DS97Z8X0502 Zilog ...
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... Zilog Table 6. 44-Pin LQFP Pin Configuration Table 6. 44-Pin QFP Pin Identification EPROM Programming Mode EPROM Programming Mode Pin # Symbol Function 1–2 A5–A6 Address 5,6 3– Connection 5 A7 Address 7 6–7 V Power Supply CC 8– Connection 11 CE Chip Select 12 OE Output Enable ...
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... A10 V A11 28-Pin DIP/SOIC Pin Configuration P05 5 25 XXX P21 P06 P20 XXX P07 P03 XXX 28-Pin PLCC V XXX XXX XT2 P02 XXX XT1 P01 11 19 XXX P31 P00 12 18 Figure 11. Standard Mode 28-Pin PLCC Pin Configuration DS97Z8X0502 Zilog ...
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... Zilog XXX A5 XXX A6 XXX A7 28-Pin PLCC VCC XXX XXX NC XXX CE 11 XXX OE 12 Figure 12. EPROM Programming Mode 28-Pin PLCC Pin Configuration DS97Z8X0502 Pin # Symbol 1–3 D5–D7 4–7 A4– XXX XXX 10 CE XXX XXX EPM XXX A2 XXX XXX A0 18 14–15 A8–A9 ...
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... Power dissipation is calculated as follows: Total Power Dissipation = V + sum sum of (V From Output Under Test Min Max –40 +105 –65 +150 –0.6 +7 –0.3 +7 –0 1.21 220 180 –600 +600 –600 +600 – (sum – 150 pF Figure 13. Test Load Diagram DS97Z8X0502 Zilog Units ...
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... Zilog CAPACITANCE GND = 0V 1.0 MHz; unmeasured pins returned to GND Parameter Min Input capacitance 0 Output capacitance 0 I/O capacitance 0 DC ELECTRICAL CHARACTERISTICS Sym Parameter V Clock Input High Voltage CH V Clock Input Low Voltage CL V Input High Voltage IH V Input Low Voltage IL V Output High Voltage ...
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... CC Typical @ 25 C Units Conditions MHz MHz MHz 2.9 mA Clock Divide by 2 MHz 0V 0V 600 0V 600 0V 2 <V < 4 <V < -1.8 A 0V<V < -3.8 A 0V<V < 2.9 V DS97Z8X0502 Zilog Notes 4,5 4,5 4,5 4,5 4,5 4,5 6,11 6,11 6,11,1 4 6,11 1,7 ...
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... Zilog V Sym Parameter Note [3] V Clock Input High 4.5V CH Voltage 5.5V V Clock Input Low 4.5V CL Voltage 5.5V V Input High Voltage 4.5V IH 5.5V V Input Low Voltage 4.5V IL 5.5V V Output High 4.5V OH Voltage Low EMI 5.5V Mode V Output High Voltage 4.5V OH1 4.5V ...
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... Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating. 12. Typicals are 5.0V CC 13. Z86E40 only 14. WDT is not running =– +105 Min Max -1.0 -10 -1.0 -10 2.0 14 2.0 14 2.0 3.3 0.5V Typical @ 25 C Units Conditions -3 < V < -3 < V < 2.9 V DS97Z8X0502 Zilog Notes ...
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... Zilog R Port 0 18 Port (Read) Port1 rite) Figure 14. External I/O or Memory Read/Write Timing DS97Z8X0502 OUT 14 Z86E40 Only Z86E30/E31/E40 Z8 4K OTP Microcontroller ...
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... Zilog Max Units Notes 180 ns 1,2 180 230 ...
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... Zilog No Symbol Parameter 1 TdA(AS) Address Valid to AS Rise Delay 2 TdAS(A) ASAS Rise to Address Float Delay 3 TdAS(DR) AS Rise to Read Data Req’d Valid 4 TwAS AS Low Width 5 TdAS(DS) Address Float to DS Fall 6 TwDSR DS (Read) Low Width 7 TwDSW DS (Write) Low Width 8 TdDSR(DR) DS Fall to Read Data Req’d ...
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... Z86E30/E31/E40 Z8 4K OTP Microcontroller DC ELECTRICAL CHARACTERISTICS (Continued) Clock 7 7 TIN 4 IRQN 8 Clock Setup Stop Mode Recovery Source Figure 15. Additional Timing Diagram Zilog DS97Z8X0502 ...
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... Zilog Additional Timing Table (Divide-By-One Mode) No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise & Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer Input Period 7 TrTin, TfTin Timer Input Rise & ...
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... Data In Valid Data (Input) RDY (Output) Data Out 7 DAV (Output) RDY (Input Delayed DAV 4 Figure 16. Input Handshake Timing Data Out Valid Figure 17. Output Handshake Timing Next Data In Valid 5 6 Delayed RDY Next Data Out Valid Delayed DAV 11 Delayed RDY DS97Z8X0502 Zilog ...
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... Zilog Additional Timing Table No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise & Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer Input Period 7 TrTin, TfTin Timer Input Rise & Fall Timer ...
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... GND, disables the internal ROM and forces the device to function as a Z86C90/C89 ROMless Z8. (Note that, when left unconnected or pulled High to V tions normally ROM version). , CE, EPM, PP Note: When using in ROM Mode in High EMI (noisy) envi- ronment, the ROMless pins should be connected directly Zilog , the device func- CC DS97Z8X0502 ...
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... Zilog Port 0 (P07–P00). Port 8-bit, bidirectional, CMOS- compatible I/O port. These eight I/O lines can be config- ured under software control as a nibble I/O port address port for interfacing external memory. The input buffers are Schmitt-triggered and nibble programmed. Ei- ther nibble output that can be globally programmed as push-pull or open-drain ...
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... Port 1 can be placed in the high-impedance state along with Port 0, AS, DS, and R/W, allowing the Z86E40 to share common resources in multiprocessor and DMA ap- plications. Port 2 (I/O) MCU Handshake Controls DAV1 and RDY1 (P33 and P34) 2.3V Hysteresis R 500 k Figure 19. Port 1 Configuration (Z86E40 Only Zilog PAD Auto Latch DS97Z8X0502 ...
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... Zilog Port 2 (P27–P20). Port 8-bit, bidirectional, CMOS- compatible I/O port. These eight I/O lines can be config- ured under software control as an input or output, indepen- dently. All input buffers are Schmitt-triggered. Bits pro- grammed as outputs can be globally programmed as either push-pull or open-drain. Low EMI output buffers can ...
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... IRQ register bits must be cleared after enabling analog mode. Note: P33–P30 differs from the Z86C30/C31/C40 in that there is no clamping diode to V voltage circuits. Exceeding the V during standard operating mode may cause the device to enter EPROM mode. ) and P36 Zilog due to the EPROM high- CC maximum specification IH DS97Z8X0502 ...
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... Zilog P30 P31 (AN1) P32 (AN2) P33 (REF) From Stop Mode Recovery Source Pin I/O CTC1 P30 IN P31 P32 IN P33 IN P34 OUT P35 OUT P36 OUT T OUT P37 OUT DS97Z8X0502 Z86E40 Port 3 MCU (I/O or Control) Auto Latch R 500 K R247 = P3M 1 = Analog ...
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... MHz – 250 ns cycle time, when Low EMI Oscillator is selected and system clock (SCLK = XTAL, SMR Reg. Bit D1 =1). Note for emulation only: Do not set the emulator to emulate Port 1 in low EMI mode. Port 1 must always be configured in Standard Mode Zilog DS97Z8X0502 ...
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... Zilog FUNCTIONAL DESCRIPTION The MCU incorporates the following special functions to enhance the standard Z8 architecture to provide the user with increased design flexibility. RESET. The device is reset in one of three ways: 1. Power-On Reset 2. Watch-Dog Timer 3. STOP-Mode Recovery Source Note: Having the Auto Power-On Reset circuitry built-in, the MCU does not need to be connected to an external power-on reset circuit ...
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... The state of the DM signal is controlled by the type of in- struction being executed. An LDC opcode references PROGRAM (DM inactive) memory, and an LDE instruction references data (DM active Low) memory. EPROM External Data Memory Not Addressable Figure 23. Data Memory Map ROMless External Data Memory DS97Z8X0502 Zilog ...
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... Zilog Register File. The register file consists of three I/O port registers, 236/125 general-purpose registers, 15 control and status registers, and three system configuration regis- ters in the expanded register group. The instructions can access registers directly or indirectly through an 8-bit ad- dress field. This allows a short 4-bit register address using the Register Pointer (Figure 24) ...
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... "0" in Register R253 (RP). Figure 25. Register Pointer R253 (Register Pointer) Note: Registers 80H through EFH are available in the Z86C30 only. The lower nibble of the register file address provided by the instruction points to the specified register. R15 to R0 R15 to R4 R0* DS97Z8X0502 Zilog ...
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... Zilog REGISTER POINTER Working Register Group Pointer Z8 Reg. File %FF %FO Z86E30/E40 Only Z86E30/E40 Only %7F %0F %00 Notes Unknown † For Z86E40 (ROMless) reset condition: "10110110" * Will not be reset with a STOP Mode Recovery ** Will not be reset with a STOP Mode Recovery, except Bit D0. ...
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... Port 3 line P36 serves as a timer output (T or the internal clock can be output. The counter/timers can be cascaded by connecting the T0 output to the input of T1 Zilog ) through which T0, T1, OUT DS97Z8X0502 ...
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... Zilog OSC D1 (SMR (SMR) 16 Internal Clock External Clock Clock Logic 4 Internal Clock Gated Clock Triggered Clock TIN P31 DS97Z8X0502 Internal Data Bus Write Write PRE0 Initial Value Register 6-Bit 4 Down Counter 6-Bit Down Counter PRE1 Initial Value Register Write Write Internal Data Bus Figure 27 ...
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... Enable Priority Logic Vector Select Figure 28. Interrupt Block Diagram Vector Location 10 Interrupt IRQ (D6, D7) Edge Select 6 Comments External (P32), Rising/Falling Edge Triggered External (P33), Falling Edge Triggered External (P31), Rising/Falling Edge Triggered External (P30), Falling Edge Triggered Internal Internal DS97Z8X0502 Zilog ...
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... Zilog When more than one interrupt is pending, priorities are re- solved by a programmable priority encoder that is con- trolled by the Interrupt Priority Register (IPR). An interrupt machine cycle is activated when an interrupt request is granted. Thus, disabling all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that in- terrupt ...
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... Port 2 Low EMI 1 Port 2 Standard* 0 Port 3 Low EMI 1 Port 3 Standard* Low EMI Oscillator 0 Low EMI 1 Standard* Figure 30. Port Configuration Register (PCON) (Write Only Zilog NOP ; clear the pipeline STOP ; enter STOP Mode or NOP ; clear the pipeline HALT ; enter HALT Mode ...
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... Zilog Comparator Output Port 3 (D0). Bit 0 controls the com- parator output in Port 3. A “1” in this location brings the comparator outputs to P34 and P37, and a “0” releases the Port to its standard I/O configuration. The default value is 0. Port 1 Open-Drain (D1). Port 1 can be configured as an open-drain by resetting this bit (D1=0) or configured as push-pull active by setting this bit (D1=1) ...
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... P30 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0:3 111 P2 NOR 0:7 Stop Delay 0 OFF 1 ON Stop Recovery Level 0 Low 1 High Stop Flag 0 POR 1 Stop Recovery Figure 31. STOP-Mode Recovery Register (Write-Only Except Bit D7, Which is Read-Only DS97Z8X0502 Zilog ...
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... Zilog SCLK/TCLK Divide-by-16 Select (D0). This bit of the SMR controls a divide-by-16 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers and interrupt logic). External Clock Divide-by-Two (D1). This bit can elimi- nate the oscillator divide-by-two circuitry ...
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... WDT will not run in STOP mode. Note: WDT time-out in STOP Mode will not reset SMR,SMR2,PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data Registers. WDTMR Register Accessibility. The WDTMR register is accessible only during the first 60 internal system clock Zilog Time-out of Time-out of the Internal the System RC OSC Clock ...
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... Zilog cycles from the execution of the first instruction after Power-On Reset, Watch-Dog reset or a STOP-Mode Recovery (Figures 33 and 34). After this point, the register cannot be modified by any means, intentional or WDTMR ( Default setting after RESET DS97Z8X0502 otherwise. The WDTMR cannot be read and is located in Bank F of the Expanded Register Group at address location 0FH ...
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... From Stop Mode Recovery Source Stop Delay Select (SMR) 46 Clear 18 Clock RESET Generator CLK WDT TAP SELECT 5ms POR 5ms M CK WDT/POR Counter Chain U CLR X 2V Operating Voltage Det. Figure 34. Resets and WDT RESET 15ms 25ms 100ms DS97Z8X0502 Zilog Internal RESET ...
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... Zilog Auto Reset Voltage. An on-board Voltage Comparator checks that the required level to ensure correct CC operation of the device. Reset is globally driven if V below V (Figure 35). LV 3.7 VCC (Volts) 3.5 3.3 3.1 2.9 2.7 2.5 2.3 -60 Figure 35. Typical Z86E40 V DS97Z8X0502 Note the minimum Power-On Reset time-out (T ...
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... Binary). The Options are mapped into this address as follows: Bit Table 14 gives the proper conditions for EPROM R/W op- erations, once the mode is latched. LSB Addr 0000 0011 Zilog Option Unused Unused 32 KHz XTAL Option Permanent WDT Auto Latch Disable RC Oscillator Option RAM Protect ROM Protect DS97Z8X0502 ...
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... NU = Not used, but must be set to either V I during programming = 40 mA maximum during programming, verify, or read = 40 mA maximum has a tolerance of 0.25V. CC † Zilog recommends an EPROM read at V ensure proper device operations during the V but acceptable. CC Parameters Name 1 Address Setup Time 2 Data Setup Time ...
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... Z8 4K OTP Microcontroller FUNCTIONAL DESCRIPTION (Continued) VIH Address VIL VIH Data VIL VH VPP VIL VH EPM VIL V CC 4.5V VIH CE VIL VIH OE VIL VIH PGM VIL 50 Address Stable 16 Invalid Valid Invalid Figure 36. EPROM Read Mode Timing Diagram Address Stable Valid 5.5V 15 DS97Z8X0502 Zilog ...
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... Zilog Z86E40 TIMING DIAGRAMS V IH Address Data EPM 4. PGM V IL Figure 37. Timing Diagram of EPROM Program and Verify Modes DS97Z8X0502 Address Stable 1 Data Stable Program Cycle Z86E30/E31/E40 Z8 4K OTP Microcontroller Data Out Valid Verify Cycle 1 51 ...
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... R2 1 KOhm 1 A10 R1 1 KOhm A11 1 GND 12. EPM GND 5.0 V VCC For use with Standard EPROM Programmers A10 21 A10 A11 23 A11 2 A12 27 GND PGM 14 GND VCC 2764 Pins KOhm 1 KOhm GND 5.0V 1 KOhm GND DS97Z8X0502 Zilog VPP 0.01 F GND 12.5 Volt 2 ...
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... Zilog P20 25 D1 P21 D2 26 P22 D3 27 P23 D4 28 P24 D5 1 P25 D6 2 P26 D7 3 P27 P30 P00 P31 P01 P32 P02 P33 P03 P34 P04 P35 P05 P36 P06 P37 P07 10 XTAL1 XTAL2 Z86E30/31 28-Pin DIP Socket U3 12. GND 4 X3 ...
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... Zilog Note ensure proper operaton, Zilog recommends Vcc range of the device Vcc specification, But Vcc = 5.0V is acceptable. DS97Z8X0502 Start Addr = First Location Vcc = 6.4 V Vpp = 13 Program 1 ms Pulse Increment Fail Verify One Byte Pass Prog. One Pulse 3xN ms Duration No Increment Last Addr ? ...
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... Default setting after RESET 1 Port 3 Standard* Low EMI Oscillator 0 Low EMI Figure 43. Watch-Dog Timer Mode Register 1 Standard* SMR2 (0F Note: Not used in conjunction with SMR Source Figure 44. STOP-Mode Recovery Register Zilog WDT TAP INT RC OSC System Clock 128 SCLK 256 SCLK * 512 SCLK ...
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... Zilog Z8 CONTROL REGISTER DIAGRAMS R240 Figure 45. Reserved R241 TMR Default After Reset = 00H Figure 46. Timer Mode Register F1H: Read/Write R242 Figure 47. Counter/Timer 1 Register F2H: Read/Write DS97Z8X0502 R243 PRE1 D7 D6 Reserved (Must be 0) *Default After Reset 0 No Function* 1 Load T0 0 Disable T0 Count* ...
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... Reserved IRQ1, IRQ4 Priority (Group C) 0 IRQ1 > IRQ4 1 IRQ4 > IRQ1 IRQ0, IRQ2 Priority (Group B) 0 IRQ2 > IRQ0 1 IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 IRQ5 > IRQ3 1 IRQ3 > IRQ5 Reserved (Must be 0) Figure 54. Interrupt Priority Register F9H: Write Only DS97Z8X0502 Zilog ...
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... Zilog R250 IRQ Default After Reset = 00H Figure 55. Interrupt Request Register FAH: Read/Write R251 IMR † This option must be selected when ROM code is submitted for ROM Masking, otherwise this control bit is disabled permanently. Figure 56. Interrupt Mask Register FBH: Read/Write R252 FLAGS Figure 57 ...
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... Z86E30/E31/E40 Z8 4K OTP Microcontroller PACKAGE INFORMATION (Continued) PACKAGE INFORMATION 60 Figure 61. 40-Pin DIP Package Diagram Zilog DS97Z8X0502 ...
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... Zilog DS97Z8X0502 Figure 62. 44-Pin PLCC Package Diagram Figure 63. 44-Pin LQFP Package Diagram Figure 63. 44-Pin QFP Package Diagram Z86E30/E31/E40 Z8 4K OTP Microcontroller 1 61 ...
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... Z86E30/E31/E40 Z8 4K OTP Microcontroller 62 Figure 64. 28-Pin DIP Package Diagram Figure 65. 28-Pin SOIC Package Diagram Zilog DS97Z8X0502 ...
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... Zilog DS97Z8X0502 Figure 66. 28-Pin PLCC Package Diagram Z86E30/E31/E40 Z8 4K OTP Microcontroller 1 63 ...
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... Z86E31 (16 MHz) 28-Pin DIP 28-Pin SOIC Z86E3116PSC Z86E3116SSC Z86E3116PEC Z86E3116SEC For fast results, contact your local Zilog sales office for assistance in ordering the part desired. Package P = Plastic DIP V = Plastic Leaded Chip Carrier F = Plastic Quad Flat Pack S = SOIC (Small Outline Integrated Circuit) Example: ...
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... Zilog, Inc. The information in this document is subject to change For answers to technical questions about the product, documentation, or any other issues with Zilog’s offerings, please without notice. Devices sold by Zilog, Inc. are covered by visit Zilog’s Knowledge Base at http://www.zilog.com/kb. ...