EM35X-DEV-UPG-IAR Ember, EM35X-DEV-UPG-IAR Datasheet - Page 93

• Manufacturer Part Number: EM35X-DEV-UPG-IAR
• Description: IAR EWARM LICENCE FOR EM35X
• Manufacturer: Ember
• Type: Licenser

Specifications of EM35X-DEV-UPG-IAR

• For Use With/related Products: EM35x
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1028

8.5
TWI - Two Wire serial Interfaces
8.4.6
Refer to Registers (in the SPI Master Mode section) for a description of the SCx_DATA, SCx_SPICFG, and
SCx_SPISTAT registers.
Both EM35x serial controllers SC1 and SC2 include a Two Wire serial Interface (TWI) master controller with the
following features:
8.5.1
The TWI master controller uses just two signals:
Table 8-7 lists the GPIO pins used by the SC1 and SC2 TWI master controllers. Because the pins are configured
as open-drain outputs, they require external pull-up resistors.
8.5.2
The TWI controller is enabled by writing 3 to the SCx_MODE register. The TWI controller operates only in
master mode and supports both Standard (100 kbps) and Fast (400 kbps) TWI modes. Address arbitration is not
implemented, so multiple master applications are not supported.
The TWI master controller’s serial clock (SCL) is produced by a programmable clock generator. SCL is
produced by dividing down 12 MHz according to this equation:
Uses only two bidirectional GPIO pins
Programmable clock frequency (up to 400 kHz)
Supports both 7-bit and 10-bit addressing
Compatible with Philips’ I
SDA (Serial Data) – bidirectional serial data
SCL (Serial Clock) – bidirectional serial clock
GPIO Configuration
Registers
GPIO Usage
Set Up and Configuration
Direction
SC1 pin
SC2 pin
rate
2
C-bus slave devices
=
(
LIN
Table 8-7. TWI Master GPIO Usage
12
+
Final
8-18
MHz
1
* )
Alternate Output
Input / Output
2
(open drain)
EXP
SDA
PA1
PB1
EM351 / EM357
Alternate Output
Input / Output
(open drain)
SCL
PB2
PA2
120-035X-000G