74AHC08 NXP Semiconductors, 74AHC08 Datasheet
74AHC08
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74AHC08 Summary of contents
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... Quad 2-input AND gate Rev. 03 — 14 November 2007 1. General description The 74AHC08; 74AHCT08 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74AHC08; 74AHCT08 provides the quad 2-input AND function. ...
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... Fig 1. Logic symbol 5. Pinning information 5.1 Pinning GND 001aac945 Fig 4. Pin configuration SO14 and TSSOP14 74AHC_AHCT08_3 Product data sheet 74AHC08; 74AHCT08 1 & & & & mna223 Fig 2. IEC logic symbol ...
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... O I supply current CC I ground current GND T storage temperature stg 74AHC_AHCT08_3 Product data sheet 74AHC08; 74AHCT08 Description data input data input data output data input data input data output ground (0 V) data output data input data input data output ...
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... I V output voltage O T ambient temperature amb t/ V input transition rise V and fall rate V 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions For type 74AHC08 V HIGH-level input voltage LOW-level V = 2.0 V ...
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... 3 4.4 4 1.35 2 GND 3.0 10 Rev. 03 — 14 November 2007 74AHC08; 74AHCT08 Quad 2-input AND gate + +125 C Unit Min Max Min - 2.0 - 2 4.4 - 4.4 - 3.8 - 3 © NXP B.V. 2007. All rights reserved. ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions For type 74AHC08 t propagation nA nY; see pd delay power pF ...
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... Product data sheet nA, nB input M GND t PHL output Table 8. Input V M 0.5V CC 1.5 V Rev. 03 — 14 November 2007 74AHC08; 74AHCT08 Quad 2-input AND gate t PLH mna224 Output V M 0.5V CC 0.5V CC © NXP B.V. 2007. All rights reserved ...
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... DUT the pulse generator. o Load pF pF Rev. 03 — 14 November 2007 74AHC08; 74AHCT08 Quad 2-input AND gate open C L 001aad983 S1 position ...
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... 0.49 0.25 8.75 4.0 6.2 1.27 1.05 0.36 0.19 8.55 3.8 5.8 0.0100 0.35 0.16 0.244 0.05 0.041 0.0075 0.34 0.15 0.228 REFERENCES JEDEC JEITA MS-012 Rev. 03 — 14 November 2007 74AHC08; 74AHCT08 Quad 2-input AND gate detail 1.0 0.7 0.7 0.25 0.25 0.1 0.4 0.6 0.3 0.039 0.028 ...
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... 2 scale (1) ( 0.30 0.2 5.1 4.5 6.6 0.65 0.19 0.1 4.9 4.3 6.2 REFERENCES JEDEC JEITA MO-153 Rev. 03 — 14 November 2007 74AHC08; 74AHCT08 Quad 2-input AND gate detail 0.75 0.4 0.72 1 0.2 0.13 0.1 0.50 0.3 0.38 EUROPEAN ISSUE DATE ...
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... D max. 0.05 0.30 3 0.2 0.00 0.18 2.9 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION IEC SOT762 Fig 10. Package outline SOT762-1 (DHVQFN14) 74AHC_AHCT08_3 Product data sheet 74AHC08; 74AHCT08 2.5 scale ...
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... Section 74AHC_AHCT08_2 19990924 74AHC_AHCT08_1 19981218 74AHC_AHCT08_3 Product data sheet 74AHC08; 74AHCT08 Data sheet status Product data sheet 3: DHVQFN14 package added. 7: derating values added for DHVQFN14 package. 12: outline drawing added for DHVQFN14 package. Product specification Product specification Rev. 03 — 14 November 2007 ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 14 November 2007 74AHC08; 74AHCT08 Quad 2-input AND gate © NXP B.V. 2007. All rights reserved ...
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... Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 16 Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 74AHC08; 74AHCT08 Quad 2-input AND gate Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp ...