74AHC00PW,112 NXP Semiconductors, 74AHC00PW,112 Datasheet
74AHC00PW,112
Specifications of 74AHC00PW,112
74AHC00PW
935262687112
Related parts for 74AHC00PW,112
74AHC00PW,112 Summary of contents
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Quad 2-input NAND gate Rev. 04 — 28 April 2008 1. General description The 74AHC00; 74AHCT00 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL specified in compliance with JEDEC ...
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... NXP Semiconductors Table 1. Ordering information Type number Package Temperature range Name 74AHCT00 74AHCT00D +125 C 74AHCT00PW +125 C 74AHCT00BQ +125 C 4. Functional diagram mna212 Fig 1. Logic symbol 5. Pinning information 5.1 Pinning GND 7 Fig 4. Pin configuration SO14 and TSSOP14 74AHC_AHCT00_4 Product data sheet … ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin GND Functional description [1] Table 3. Function selection Input [ HIGH voltage level LOW voltage level don’t care. 74AHC_AHCT00_4 Product data sheet Description data input data input data output data input data input ...
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... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I I input clamping current IK I output clamping current OK I output current O I supply current ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74AHC00 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage GND current supply current input capacitance V ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I supply current additional supply per input pin; CC current other pins input capacitance 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see ...
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... NXP Semiconductors 11. Waveforms Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 6. Input to output propagation delays Table 8. Measurement points Type 74AHC00 74AHCT00 Test data is given in Table Definitions test circuit termination resistance should be equal to output impedance Z ...
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... NXP Semiconductors Table 9. Test data Type Input V I 74AHC00 V CC 74AHCT00 3.0 V 74AHC_AHCT00_4 Product data sheet 74AHC00; 74AHCT00 Load Rev. 04 — 28 April 2008 Quad 2-input NAND gate Test PLH PHL PLH PHL © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charge Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 14 Revision history ...