74AHC574BQ,115 NXP Semiconductors, 74AHC574BQ,115 Datasheet
74AHC574BQ,115
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74AHC574BQ-G
935285546115
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74AHC574BQ,115 Summary of contents
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Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 02 — 24 January 2008 1. General description The 74AHC574; 74AHCT574 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74AHC574D +125 C 74AHCT574D 74AHC574PW +125 C 74AHCT574PW 74AHC574BQ +125 C 74AHCT574BQ 4. Functional diagram Fig 1. Functional diagram FF1 Fig 2. Logic diagram 74AHC_AHCT574_2 Product data sheet Octal D-type flip-flop; positive edge-trigger; 3-state ...
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... NXP Semiconductors Fig 3. Logic symbol 74AHC_AHCT574_2 Product data sheet Octal D-type flip-flop; positive edge-trigger; 3-state mna798 Fig 4. Rev. 02 — 24 January 2008 74AHC574; 74AHCT574 mna446 IEC logic symbol © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 74AHC574 74AHCT574 GND 10 Fig 5. Pin configuration SO20, TSSOP20 5.2 Pin description Table 2. Pin description Symbol Pin OE 1 D[0: GND Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output 74AHC_AHCT574_2 Product data sheet Octal D-type flip-flop; positive edge-trigger; 3-state ...
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... NXP Semiconductors 6. Functional description [1] Table 3. Function table Operating mode Load and read register Load register and disable output [ HIGH voltage level HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition LOW voltage level LOW voltage level one setup time prior to the HIGH-to-LOW CP transition; ...
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... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V) ...
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... NXP Semiconductors Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C input I capacitance C output O capacitance For type 74AHCT574 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage 8 LOW-level output voltage 8 OFF-state per input pin output current V = 5.5 V ...
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... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V. For test circuit see Figure Symbol Parameter Conditions For type 74AHC574 t propagation CP to Qn; see pd delay enable time OE to Qn; see disable time OE to Qn; see dis maximum CP; see ...
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... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V. For test circuit see Figure Symbol Parameter Conditions t set-up time Dn to CP; see hold time Dn to CP; see power pF dissipation V = GND capacitance For type 74AHCT574 t propagation CP to Qn; see pd delay enable time ...
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... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V. For test circuit see Figure Symbol Parameter Conditions t hold time Dn to CP; see 4 5 power per buffer; PD dissipation pF MHz; L capacitance V = GND [1] Typical values are measured at nominal supply voltage (V [ the same as t and PLH PHL t is the same as t and t ...
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... NXP Semiconductors CP input Dn input Qn output Measurement points are given in V and V are typical voltage output levels that occur with the output load The shaded areas indicate when the input is permitted to change for predicable output performance. Fig 8. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times ...
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... NXP Semiconductors PULSE GENERATOR Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 10. Load circuitry for switching times Table 9. Test data Type Input 74AHC574 V 3 ...
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... NXP Semiconductors 11. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... Document ID Release date 74AHC_AHCT574_2 20080124 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section • Section • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 10.1 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 13 Revision history ...