74AHC541PW,112 NXP Semiconductors, 74AHC541PW,112 Datasheet
74AHC541PW,112
Specifications of 74AHC541PW,112
74AHC541PW
935262008112
Related parts for 74AHC541PW,112
74AHC541PW,112 Summary of contents
Page 1
Octal buffer/line driver; 3-state Rev. 03 — 12 November 2007 1. General description The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device. The 74AHC541; 74AHCT541 are octal non-inverting buffer/line drivers with 3-state bus compatible outputs. The 3-state outputs ...
Page 2
... NXP Semiconductors 4. Functional diagram Fig 1. Logic symbol 74AHC_AHCT541_3 Product data sheet 74AHC541; 74AHCT541 mna179 Fig 2. IEC logic symbol Rev. 03 — 12 November 2007 Octal buffer/line driver; 3-state 1 & mna180 © NXP B.V. 2007. All rights reserved ...
Page 3
... NXP Semiconductors 5. Pinning information 5.1 Pinning 74AHC541 74AHCT541 1 OE0 GND 10 Fig 3. Pin configuration SO20, TSSOP20 5.2 Pin description Table 2. Pin description Symbol Pin OE0 1 A[0: GND 10 Y[0:7] 18, 17, 16, 15, 14, 13, 12, 11 data output OE1 74AHC_AHCT541_3 Product data sheet OE1 18 Y0 ...
Page 4
... NXP Semiconductors 6. Functional description [1] Table 3. Functional table Control OE0 OE1 [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
Page 5
... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V) ...
Page 6
... NXP Semiconductors Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions C input I capacitance C output O capacitance For type 74AHCT541 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage 8 LOW-level output voltage 8 OFF-state per input pin output current V = 5.5 V ...
Page 7
... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V. For test circuit see Figure Symbol Parameter Conditions For type 74AHC541 t propagation An to Yn; see pd delay enable time OEn to Yn; see disable time OEn to Yn; see dis 3.6 V ...
Page 8
... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V. For test circuit see Figure Symbol Parameter Conditions For type 74AHCT541 t propagation An to Yn; see pd delay enable time OEn to Yn; see 4 5 disable time OEn to Yn; see dis power per buffer; PD dissipation pF MHz; ...
Page 9
... NXP Semiconductors 11. Waveforms Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 5. Propagation delay input (An) to output (Yn) OEn input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical voltage output levels that occur with the output load. ...
Page 10
... NXP Semiconductors PULSE GENERATOR Test data is given in Table 9. Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistor Test selection switch Fig 7. Load circuitry for switching times Table 9. Test data Type Input ...
Page 11
... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
Page 12
... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 13
... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
Page 14
... Document ID Release date 74AHC_AHCT541_3 20071112 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section • Section • ...
Page 15
... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 16
... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 Revision history ...