74hc4852bq NXP Semiconductors, 74hc4852bq Datasheet
74hc4852bq
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74hc4852bq Summary of contents
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Dual 4-channel analog multiplexer/demultiplexer with injection-current effect control Rev. 02 — 30 May 2007 1. General description The 74HC4852 is a high-speed Si-gate CMOS device and is specified in compliance with JEDEC standard no. 7A. The 74HC4852 is a ...
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... Digital multiplexing and demultiplexing I Signal gating I Automotive application 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74HC4852D +125 C 74HC4852PW +125 C 74HC4852BQ +125 C 5. Functional diagram Fig 1. Logic symbol 74HC4852_2 Product data sheet ...
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... NXP Semiconductors Fig 3. Functional diagram 74HC4852_2 Product data sheet 4-channel analog MUX/DEMUX with injection-current effect control 1-OF-4 DECODER GND 8 Rev. 02 — 30 May 2007 74HC4852 INJECTION 13 1Z CURRENT CONTROL INJECTION 12 1Y0 CURRENT CONTROL INJECTION 14 1Y1 CURRENT CONTROL INJECTION 15 1Y2 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning 74HC4852 2Y0 1 2Y2 2Y3 4 2Y1 n.c. GND 8 Fig 4. Pin configuration SO16 and TSSOP16 6.2 Pin description Table 2. Pin description Symbol Pin 2Y0 1 2Y2 2Y3 4 2Y1 n.c. 7 GND 1Y3 11 1Y0 12 1Z ...
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... NXP Semiconductors 7. Functional description [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level don’t care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW T ambient temperature amb t/ V input transition rise and fall rate 10. Static characteristics Table resistance For test circuit see Figure 8. Symbol ...
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... NXP Semiconductors Table 6. R …continued ON resistance For test circuit see Figure 8. Symbol Parameter R ON resistance mismatch between ON channels +125 C amb R ON resistance (peak) ON(peak resistance mismatch between ON channels Table 7. Injection current coupling For test circuit see Figure 9. Symbol ...
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... NXP Semiconductors Table 8. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter amb V HIGH-level input voltage IH V LOW-level input voltage IL I input leakage current I I OFF-state leakage current S(OFF) I ON-state leakage current S(ON) I supply current CC C input capacitance I C switch capacitance ...
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... NXP Semiconductors Table 8. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter I input leakage current I I OFF-state leakage current S(OFF) I ON-state leakage current S(ON) I supply current CC C input capacitance I C switch capacitance +125 C amb V HIGH-level input voltage IH V LOW-level input voltage ...
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... NXP Semiconductors Table 8. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter C input capacitance I C switch capacitance nYn A GND V I Fig 6. Test circuit for measuring OFF-state leakage current nYn GND ...
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... NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics GND = pF unless specified otherwise; for test circuit see L L Symbol Parameter Conditions propagation delay see pd nZ, nYn to nYn nZ, nYn t enable time see nZ, nYn ...
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... NXP Semiconductors Table 9. Dynamic characteristics GND = pF unless specified otherwise; for test circuit see L L Symbol Parameter Conditions propagation delay see pd nZ, nYn to nYn nZ, nYn t enable time see nZ, nYn t disable time ...
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... NXP Semiconductors E input nZ or nYn output nZ or nYn output Test data is given in Table 10. Logic levels: V and V are typical output voltage levels that occur with the output load Fig 11. Enable and disable times Table 10. Measurement points Supply voltage Input 2 6.0 V ...
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... NXP Semiconductors a. Input pulse definition Definitions for test circuit load resistance load capacitance including jig and probe capacitance termination resistance should be equal to the output impedance Load circuitry Test data is given in Table 11. Fig 12. Load circuitry for switching times Table 11. ...
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... NXP Semiconductors 13. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 13. Revision history Document ID Release date 74HC4852_2 20070530 • Modifications: Typo corrected (“ ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 11 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 14 Abbreviations ...