AD679 Analog Devices, AD679 Datasheet
AD679
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AD679 Summary of contents
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... The AD679 operates from +5 V and 12 V supplies and dissi- pates 560 mW (typ). 28-pin plastic DIP, ceramic DIP and 44 J-leaded ceramic surface mount packages are available. ...
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... –2– 10 128 kSPS 10.009 kHz DD SAMPLE IN AD679K/B/T Max Min Typ Max –84 –90 –84 0.006 0.003 0.006 –82 –88 –82 0.008 0.004 0.008 –84 –90 – ...
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... FSR 0.09 0.10 % FSR 0.02 0.04 % FSR 0.04 0.05 % FSR 0.08 0.09 % FSR 0.09 0.11 % FSR 0.10 0.16 % FSR 0.20 0.25 % FSR 0.04 0.05 % FSR 0.05 % FSR 0.07 0.09 0.10 % FSR 0 +10 V – 1 150 ps 4.98 5.02 V +1 LSB 6 LSB 6 LSB 560 745 and T . Results from those tests are used to MIN, MAX AD679 ...
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... For parallel read (14-bits) interface to 16-bit buses, see AD779. 2 For details grade and package offerings screened in accordance with MIL-STD- 883, refer to the Analog Devices Miliary Products Databook or current AD679/ 883B data sheet Plastic DIP Ceramic DIP J-Leaded Ceramic Chip Carrier. ...
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... The AD679 features input protection circuitry consisting of large “distributed” diodes and polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast, low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD679 has been classified as a Category 1 device. ...
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... AD679 28-Pin 44-Lead DIP JLCC Symbol Pin No. Pin No. AGND 7 11 AIN 6 10 BIPOFF DGND 12 DB7–DB0 26–19 40, 39, 37, 36, 35, 34, 33, 31 EOC 27 42 EOCEN 1 1 HBE REF REF 8 12 OUT SYNC ...
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... At this point, the amplitude of the reconstructed fundamental has degraded by less than –0.1 dB. Beyond this frequency, dis- tortion of the sampled input signal increases significantly. The AD679 has been designed to optimize input bandwidth, al- lowing it to undersample input signals with frequencies signifi- cantly above the converter’s Nyquist frequency. ...
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... The 14-bit result is left justified within the 16-bit field. In unipolar mode (BIPOFF tied to AGND), the output coding is straight binary. In bipolar mode (BIPOFF tied to REF output coding is twos-complement binary. POWER-UP The AD679 typically requires 10 s after power-up to reset in- ternal logic. STATUS No Conversion Start Conversion ...
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... INPUT CONNECTIONS AND CALIBRATION The high ( input impedance of the AD679 eases the task of interfacing to high source impedances or multiplexer channel-to-channel mismatches 300 . The 10 V p-p full-scale input range accepts the majority of signal voltages without the need for voltage divider networks which could dete- riorate the accuracy of the ADC ...
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... Figure 7 shows the use of the AD586 with the AD679 in a bipo- lar input mode. Over the +70 C range, the AD586 L-grade exhibits less than a 2.25 mV output change from its ini- tial value REF two ...
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... AD679 interface with one wait state. The converter is configured to run asynchronously using a sam- pling clock. The EOC output of the AD679 gets asserted at the end of each conversion and causes an interrupt. Upon interrupt, the ADSP-2101 immediately asserts its FO pin LOW. In the following cycle, the processor starts a data memory read by pro- viding an address on the DMA bus ...
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... AD679 Figure 13. Harmonic Distortion vs. Input Frequency (–0.5 dB Input) Figure 14. Total Harmonic Distortion vs. Input Frequency and Amplitude Figure 15. S/(N+D) vs. Input Frequency and Amplitude Figure 16. 5-Plot Averaged 2048 Point FFT at 128 kSPS 10.009 kHz IN Figure 17. Nonaveraged IMD Plot for 9.58 kHz ( 128 kSPS ...