ADUC834 Analog Devices, ADUC834 Datasheet
ADUC834
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ADUC834 Summary of contents
Page 1
... On-chip factory firmware supports in-circuit serial download and debug modes (via UART), as well as single-pin emulation mode via the EA pin. The ADuC834 is supported by a QuickStart™ development system featuring low cost software and hardware development tools. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...
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... Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 - Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ADC Chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 NONVOLATILE FLASH/EE MEMORY Flash/EE Memory Overview . . . . . . . . . . . . . . . . . . . . . . 28 Flash/EE Memory and the ADuC834 . . . . . . . . . . . . . . . 28 ADuC834 Flash/EE Memory Reliability . . . . . . . . . . . . . 29 Flash/EE Program Memory . . . . . . . . . . . . . . . . . . . . . . . 30 Serial Downloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Parallel Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 User Download Mode (ULOAD Flash/EE Program Memory Security . . . . . . . . . . . . . . . . 31 Lock, Secure, and Serial Safe Modes . . . . . . . . . . . . . . . . 31 Using the Flash/EE Data Memory ...
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... Programmable in 0.732 ms Increments Update Rate 13.5 Range = ± Update Rate 18.5 Range = ± 2. Update Rate See Tables X and XI Output Noise Varies with Selected in ADuC834 ADC Update Rate and Gain Range Description ± LSB 16 ± 3 ± 10 ± 10 ± 0.5 ± ...
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... ANALOG (DAC) OUTPUT Voltage Range Resistive Load Capacitive Load Output Impedance I SINK TEMPERATURE SENSOR Accuracy Thermal Impedance ( ) JA ADuC834 Test Conditions/Comments 1.25 ± 1% Initial Tolerance @ 25° 100 2.5 ± 1% Initial Tolerance @ 25° ± 100 9, 10 External Reference Voltage = 2.5 V RN2, RN1, RN0 of ADC0CON Set to ± ...
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... All Digital Inputs –5– ADuC834 Unit nA typ nA typ % typ %/°C typ A typ % typ ppm/°C typ % typ ppm/°C typ A/V typ A/V typ V max min V max V max V min V min/V max V min/V max ...
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... Wake-Up with SPI Interrupt Wake-Up with TIC Interrupt Wake-Up with External RESET Oscillator Powered Down Wake-Up with INT0 Interrupt Wake-Up with SPI Interrupt Wake-Up with External RESET FLASH/EE MEMORY RELIABILITY CHARACTERISTICS 16 Endurance 17 Data Retention ADuC834 Test Conditions/Comments 2 2 SOURCE 2 SOURCE 0 ...
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... MAX 125°C; Osc. On, TIC On MAX 10 Osc. Off 5. Osc. Off 5. Osc. Off –7– ADuC834 Unit Can Be Set Independently DD V min V max V min V max V min V max V min V max = 5. max mA typ mA max A max A typ ...
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... REF REF 12 The ADuC834BCP (CSP Package) has been qualified and tested with the base of the CSP Package floating. 13 Pins configured in SPI Mode, pins configured as digital inputs during this test Pins configured Mode only ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC834 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... REFIN 200 A 200 A IEXC 1 CURRENT SOURCE MUX IEXC *PIN NUMBERS REFER TO THE 52-LEAD MQFP PACKAGE SHADED AREAS REPRESENT THE NEW FEATURES OF THE ADuC834 OVER THE ADuC824 Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic 1, 2 56, 1 P1.0/P1.1 P1.0/T2/PWM0 P1.1/T2EX/PWM1 I ...
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... Serial Data I/O for the I C Interface or Master Output/Slave Input for the SPI Interface. A weak internal pull-up is present on this pin unless it is outputting logic low. This pin can also be directly controlled in software as a digital output pin. –11– ADuC834 SPI Interface input, this pin is a ...
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... ADuC834 Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic 28–31 30–33 P2.0–P2.7 36–39 39–42 (A8–A15) (A16–A23 XTAL1 33 35 XTAL2 PSEN ALE 43–46 46–49 P0.0–P0.7 49–52 52–55 (AD0–AD3) (AD4–AD7 Input Output Supply. PIN FUNCTION DESCRIPTIONS (continued) ...
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... Figure 2. Lower 128 Bytes of Internal Data Memory (4) Internal XRAM The ADuC834 contains 2 Kbytes of on-chip extended data memory. This memory, although on-chip, is accessed via the MOVX instruction. The 2 Kbytes of internal XRAM are mapped into the bottom 2 Kbytes of the external address space if the CFG834 ...
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... MOVX instruction. The MOVX instruction automatically outputs the various control strobes required to access the data memory. The ADuC834 however, can access Mbytes of external data memory. This is an enhancement of the 64 Kbytes external data memory space available on a standard 8051 compatible core. ...
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... The PCON SFR contains bits for power-saving options and general-purpose status flags as shown in Table II. The TIC (wake-up/RTC timer) can be used to accurately wake up the ADuC834 from power-down at regular intervals. To use the TIC to wake up the ADuC834 from power-down, the OSC_PD bit in the PLLCON SFR must be clear and the TIC must be enabled ...
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... ADuC834 COMPLETE SFR MAP Figure 6 shows a full SFR memory map and the SFR contents after RESET. NOT USED indicates unoccupied SFR loca- tions. Unoccupied locations in the SFR address space are not ISPI WCOL SPE SPIM CPOL CPHA FFH 0 FEH 0 FDH 0 FCH ...
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... GN0L/M/H GN1L/H Table IV. ADCSTAT SFR Bit Designations . REF –17– ADuC834 Primary ADC 24-bit conversion result is held in these three 8-bit registers. Auxiliary ADC 16-bit conversion result is held in these two 8-bit registers. Primary ADC 24-bit Offset Calibration Coefficient is held in these three 8-bit registers. ...
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... ADuC834 ADCMODE (ADC Mode Register) Used to control the operational mode of both ADCs. SFR Address D1H Power-On Default Value 00H Bit Addressable No Bit Name Description 7 ––– Reserved for Future Use 6 ––– Reserved for Future Use 5 ADC0EN Primary ADC Enable. ...
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... AGND 1 AIN4 AGND 0 Temp Sensor AGND (Temp Sensor routed to the ADC input) 1 AIN5 AGND –19– ADuC834 Auxiliary ADC Control SFR D3H 00H No = 1.25 V). REF = 2.5 V) REF (0 mV–160 mV in Unipolar Mode) (0 mV–320 mV in Unipolar Mode) (0 mV–640 mV in Unipolar Mode) ) ...
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... ADuC834 ADC0H/ADC0M/ADC0L (Primary ADC Conversion Result Registers) These three 8-bit registers hold the 24-bit conversion result from the primary ADC. SFR Address ADC0H ADC0M ADC0L Power-On Default Value 00H Bit Addressable No ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers) These two 8-bit registers hold the 16-bit conversion result from the auxiliary ADC. ...
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... Once a calibration cycle has completed, the value MOD in the SF Register will be that programmed by user software. SF(dec and conversion ADC 255 Table IX. ICON SFR Bit Designations –21– ADuC834 mentioned earlier, ADC Table VIII. SF SFR Bit Designations SF(hex) f (Hz) ADC 0D 105 ...
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... ADuC834 PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE Tables X, XI, and XII show the output rms noise in V and output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for some typical output update rates on both the primary and auxiliary ADCs. The numbers are typical and are generated at a differential input voltage ...
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... PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION Overview The ADuC834 incorporates two independent - ADCs (primary and auxiliary) with on-chip digital filtering intended for the measure- ment of wide dynamic range, low frequency signals such as those in weigh-scale, strain gage, pressure transducer, or temperature measurement applications. ...
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... ADC. When the analog input channel is switched, the settling time of the part must elapse before a new valid word is available from the ADC. DIFFERENTIAL REFERENCE THE EXTERNAL REFERENCE INPUT TO THE ADuC834 IS DIFFERENTIAL AND FACILITATES RATIOMETRIC OPERATION. THE EXTERNAL REFERENCE VOLTAGE IS SELECTED VIA THE XREF1 BIT IN ADC1CON. ...
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... For example, if AIN(–) is 2.5 V and the primary ADC is configured for an analog input range mV, the input voltage range on the AIN(+) input AIN(–) is 2.5 V and the ADuC834 is configured for an analog input range of 1.28 V, the analog input range on the AIN(+) input is 1. 3.78 V (i.e., 2.5 V ± 1.28 V). ...
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... REFIN(+) and REFIN(–) pins goes below 0 either the REFIN(+) or REFIN(–) inputs is open circuit, the ADuC834 detects that it no longer has a valid reference. In this case, the NOXREF bit of the ADCSTAT SFR is set the ADuC834 is performing normal conversions and the NOXREF bit becomes active, the conversion results revert to all 1s ...
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... The digital filter then band-limits the response to a fre- quency significantly lower than one-half of the modulator frequency. In this manner, the 1-bit output of the comparator is translated into a band-limited, low noise output from the ADuC834 ADCs. The ADuC834 filter is a low-pass, Sinc whose primary function is to remove the quantization noise introduced at the modulator ...
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... The ADuC834 provides four calibration modes that can be programmed via the mode bits in the ADCMODE SFR detailed in Table V. In fact, every ADuC834 has already been factory calibrated. The resultant Offset and Gain calibration coeffi- cients for both the primary and auxiliary ADCs are stored on-chip in manufacturing-specific Flash/EE memory locations ...
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... ADuC834 Flash/EE Memory Reliability The Flash/EE Program and Data Memory arrays on the ADuC834 are fully qualified for two key Flash/EE memory characteristics, namely Flash/EE Memory Cycling Endurance and Flash/EE Memory Data Retention ...
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... Figure 19. ULOAD mode can be used to upgrade your code in the field via any user defined download protocol. Configuring the SPI port on the ADuC834 as a slave possible to completely reprogram the 56 Kbytes of Flash/EE program memory in only 5 seconds. See Application Note uC007. ...
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... Alternatively ULOAD Mode can be used to save data to the 56 Kbytes of Flash/EE memory. This can be extremely useful in datalogging applications where the ADuC834 can provide Kbytes of NV data memory on-chip (4 Kbytes of dedicated Flash/EE data memory also exist). The upper 6 Kbytes of the 62 Kbytes of Flash/EE program memory is only programmable via serial download or parallel programming ...
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... ADuC834 Using the Flash/EE Data Memory The 4 Kbytes of Flash/EE data memory is configured as 1024 pages, each of 4 bytes. As with the other ADuC834 peripherals, the interface to this memory space is via a group of registers mapped in the SFR space. A group of four data registers (EDATA1–4) is used to hold the 4 bytes of data at each page. The page is addressed via the two registers EADRH and EADRL ...
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... Flash/EE array. This command coded in 8051 assembly would appear as: MOV ECON,#06H ; ; Flash/EE Memory Timing Typical program and erase times for the ADuC834 are as follows: Normal Mode (operating on Flash/EE data memory) READPAGE (4 bytes) WRITEPAGE (4 bytes) VERIFYPAGE (4 bytes) ERASEPAGE (4 bytes) ERASEALL (4 Kbytes) ...
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... ADuC834 DAC The ADuC834 incorporates a 12-bit, voltage output DAC on-chip. It has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF. It has two selectable ranges nal bandgap 2.5 V reference) and 12-bit or 8-bit mode. The DAC has a control register, DACCON, and two data registers, DACH/L ...
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... Figure 22. Endpoint Nonlinearities Due to Amplifier Saturation The endpoint nonlinearities conceptually illustrated in Figure 22 get worse as a function of output loading. Most of the ADuC834 data sheet specifications assume a 10 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 22 become larger ...
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... ADuC834 PULSEWIDTH MODULATOR (PWM) The PWM on the ADuC834 is a highly flexible PWM offering programmable resolution and input clock, and can be config- ured for any one of six different modes of operation. Two of these modes allow the PWM to be configured DAC with bits of resolution. A block diagram of the PWM is shown in Figure 26 ...
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... PWM1H/L, then PWM1 (P1.1) goes low and remains low until the PWM counter rolls over. In this mode, both PWM outputs are synchronized (i.e., once the PWM counter rolls over to 0, both PWM0 (P1.0) and PWM1 (P1.1) will go high). Figure 29. PWM Mode 3 –37– ADuC834 PWM1L PWM COUNTER PWM0H PWM0L PWM1H 0 P1 ...
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... ADuC834 Mode 4: Dual NRZ 16-Bit - DAC Mode 4 provides a high speed PWM output similar to that of a Σ-∆ DAC. Typically, this mode will be used with the PWM clock equal to 12.58 MHz. In this mode, P1.0 and P1.1 are updated every PWM clock ( the case of 12.58 MHz). Over any 65536 cycles (16-bit PWM) PWM0 (P1.0) is high for PWM0H/L cycles and low for (65536 – ...
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... This may be due to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output can be 12.58 MHz ± 20%. After the ADuC834 wakes up from power-down, user code may poll this bit, to wait for the PLL to lock. If LOCK = 0, then the PLL is not locked. ...
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... The time registers (HTHSEC, SEC, MIN, and HOUR) can only be written while TCEN is low. sheet.) If the ADuC834 is in power-down mode, again with TIC interrupt enabled, the TII bit will wake up the device and resume code execution by vectoring directly to the TIC interrupt service vector address at 0053H ...
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... This register is incremented in 1-hour intervals once TCEN in TIMECON is active. The HOUR SFR counts from before rolling over to 0. SFR Address A5H Power-On Default Value 00H Reset Default Value 00H if TCEN = 0, Previous Value before reset if TCEN = 1 Bit Addressable No Valid Value decimal REV. A –41– ADuC834 ...
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... ADuC834 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC834 enters an erroneous state, possibly due to a programming error, electrical noise, or RFI. The watchdog function can be disabled by clearing the WDE (Watchdog Enable) bit in the Watchdog Control (WDCON) SFR. When enabled ...
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... POWER SUPPLY MONITOR As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies ( the ADuC834. It will DD DD indicate when any of the supply pins drop below one of four user-selectable voltage trip points from 2. 4.63 V. For correct operation of the Power Supply Monitor function, AV must be equal to or greater than 2 ...
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... The data is transferred as byte-wide (8-bit) serial data, MSB first. SS (Slave Select Input Pin), Pin 13 The Slave Select (SS) input pin is only used when the ADuC834 is configured in SPI Slave mode. This line is active low. Data is only received or transmitted in Slave mode when the SS pin is low, allowing the ADuC834 to be used in single master, multislave SPI configurations ...
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... SPIDAT Register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. It should also be noted that the SS Pin is not used in Master mode. If the ADuC834 needs to assert the SS Pin on an external slave device, a port digital output pin should be used. ...
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... ADuC834 SERIAL INTERFACE The ADuC834 supports a fully licensed interface is implemented as a full hardware slave and software master. SDATA (Pin 27) is the data I/O pin and SCLOCK (Pin 26) is the serial clock. These two pins are shared with the 2 Three SFRs are used to control the I C interface ...
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... I as well as the global interrupt bit EA in the IE SFR, i.e., ; Enabling I2C Interrupts for the ADuC834 MOV SETB EA On the ADuC834 an auto clear of the I2CI bit is implemented so this bit is cleared automatically on a read or write access to the I2CDAT SFR. MOV 2 ...
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... ADuC834 DUAL DATA POINTER The ADuC834 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON). DPCON also includes features such as automatic hardware post-increment and post-decrement, as well as automatic data pointer toggle. DPCON is described in Table XXIII ...
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... SFR bit definitions. Parallel I/O The ADuC834 uses four input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations while others are multiplexed with alternate functions for the peripheral features on the device ...
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... ADuC834 P1.2 to P1.7 The remaining Port 1 pins (P1.2–P1.7) can only be configured as analog input (ADC) or digital input pins. By (power-on) default, these pins are configured as analog inputs, i.e., ‘1’ written in the corresponding Port 1 register bit. To configure any of these pins as digital inputs, the user should write a ‘0’ to these port bits to configure the corresponding pin as a high impedance digital input ...
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... Q3 *These instruction read the port byte (all 8 bits), modify the addressed bit and then write the new byte back to the latch. –51– ADuC834 DV DD HARDWARE SPI MISO ...
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... ADuC834 TIMERS/COUNTERS The ADuC834 has three 16-bit Timer/Counters: Timer 0, Timer 1, and Timer 2. The Timer/Counter hardware has been included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in soft- ware. Each Timer/Counter consists of two 8-bit registers THx and TLx ( and 2). All three can be configured to oper- ate either as timers or event counters. In ‘ ...
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... TH0 and TL0 Timer 0 high byte and low byte. SFR Address = 8CH, 8AH, respectively. TH1 and TL1 Timer 1 high byte and low byte. SFR Address = 8DH, 8BH, respectively. REV. A Table XXVII. TCON SFR Bit Designations –53– ADuC834 ...
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... ADuC834 TIMER/COUNTER 0 AND 1 OPERATING MODES The following paragraphs describe the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for Timer 0 as for Timer 1. Mode 0 (13-Bit Timer/Counter) Mode 0 configures an 8-bit timer/counter with a divide-by-32 prescaler ...
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... TL2 TH2 (8 BITS) (8 BITS CONTROL TR2 RELOAD RCAP2L RCAP2H CONTROL EXEN2 TL2 TH2 (8 BITS) (8 BITS CONTROL TR2 CAPTURE RCAP2L RCAP2H CONTROL EXEN2 Figure 53. Timer/Counter 2, 16-Bit Capture Mode –55– ADuC834 TF2 TIMER INTERRUPT EXF2 TF2 TIMER INTERRUPT EXF2 ...
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... ADuC834 T2CON Timer/Counter 2 Control Register SFR Address C8H Power-On Default Value 00H Bit Addressable Yes Bit Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 will not be set when either RCLK or TCLK = 1. Cleared by user software. 6 EXF2 Timer 2 External Flag. ...
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... Mode 2: 9-bit UART, fixed baud rate (f Mode 3: 9-bit UART, variable baud rate S1 CORE CLK ALE RxD (DATA OUT) TxD (SHIFT CLOCK) Figure 54. UART Serial Port Transmission, Mode 0 –57– ADuC834 /12) CORE /64 /32) CORE CORE MACHINE MACHINE MACHINE MACHINE CYCLE 1 CYCLE 2 ...
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... Traditionally, the baud rates in Modes 1 and 3 are determined by the overflow rate in Timer 1 or Timer 2, or both (one for transmit and the other for receive). On the ADuC834, however, the baud rate can also be generated via a separate baud rate generator to achieve higher baud rates and allow all three to be used for other functions. – ...
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... CONTROL OVERFLOW TL2 TH2 (8 BITS) (8 BITS) TR2 RELOAD RCAP2L RCAP2H TIMER 2 EXF 2 INTERRUPT CONTROL EXEN2 Figure 56. Timer 2, UART Baud Rates –59– ADuC834 ( ) ( = × 3 Baud Rate 1 16 Timer Overflow Rate f and Mode Baud Rate = × 65536 Core RCAP2H ...
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... The high integer dividers in a UART block means that high speed baud rates are not always possible using some particular crystals. e.g., using a 12 MHz crystal, a baud rate of 115200 is not possible. To address this problem the ADuC834 has added a dedicated baud rate timer (Timer 3) specifically for generating highly accurate baud rates. ...
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... INTERRUPT SYSTEM The ADuC834 provides a total of 11 interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs. These are the IE (Interrupt Enable) Register, the IP (Interrupt Priority Register) and the IEIP2 (Secondary Interrupt Enable/Priority SFR) Registers. Their bit definitions are given in the Tables XXXV – XXXVII. ...
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... ADuC834 Interrupt Priority The Interrupt Enable registers are written by the user to enable individual interrupt sources, while the Interrupt Priority registers allow the user to select one of two priority levels for each inter- rupt. An interrupt of a high priority may interrupt the service routine of a low priority interrupt, and if two interrupts of different priority occur at the same time, the higher level interrupt will be serviced first ...
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... P0, the signal ALE (Address Latch Enable) clocks this byte into an external address latch. Meanwhile, Port 2 (P2) emits the high byte of the program counter (PCH), and PSEN strobes the EPROM and the code byte is read into the ADuC834. ADuC834 P0 LATCH ...
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... The user must ensure that the power supply has reached a stable 2.7 V minimum level by this time. Likewise power-down, the internal POR will hold the ADuC834 in – reset until the power supply has dropped below 1 V. Figure 63 illustrates the operation of the internal POR in detail. ...
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... INT0 Interrupt If the INT0PD bit in the PCON SFR is set, an external interrupt 0, if enabled, will wake up the ADuC834 from power- down. The CPU services the SPI interrupt. The RETI at the end of the ISR will return the core to the instruction after that which enabled power-down ...
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... ADuC834’s digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than the ADuC834 input pins. A value of 100 Ω or 200 Ω is usually sufficient to prevent high speed signals from coupling capaci- tively into the ADuC834 and affecting the accuracy of ADC conversions ...
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... Download mode. This is accom- plished via a 1 kΩ pull-down resistor that can be jumpered onto the PSEN pin, as shown in Figure 66. To get the ADuC834 into Download mode, simply connect this jumper and power-cycle the device (or manually reset the device manual reset button is available) and it will be ready to receive a new program serially ...
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... Figure 66 also includes connections for a typical analog measure- ment application of the ADuC834, namely an interface to an RTD (Resistive Temperature Device). The arrangement shown is commonly referred 4-wire RTD configuration. Here, the on-chip excitation current sources are enabled to excite the sensor ...
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... QUICKSTART DEVELOPMENT SYSTEM The QuickStart Development System is a full featured, low cost development tool suite supporting the ADuC834. The system consists of the following PC-based (Windows hardware and software development tools. Hardware: ADuC834 Evaluation Board, and Serial Port Cable Code Development: 8051 Assembler ...
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... C LOAD 4 ADuC834 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a stable 12.583 MHz internal clock for the system. The core can operate at this frequency binary submultiple called Core_Clk, selected via the PLLCON SFR. 5 This number is measured at the default Core_Clk operating frequency of 1.57 MHz. ...
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... CORE t – CORE 4t – 100 ns CORE t – CORE 3t – CORE 3t – 105 ns CORE – CORE 5t – 105 ns CORE LLIV t PLIV t PXIZ t PXIX INSTRUCTION (IN) t PHAX ADuC834 Figure ...
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... ADuC834 Parameter EXTERNAL DATA MEMORY READ CYCLE RD Pulsewidth t RLRH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX RD Low to Valid Data In t RLDV Data and Address Hold after RD t RHDX Data Float after RD t RHDZ t ALE Low to Valid Data In ...
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... LLWL WLWH t AVWL t QVWX t LLAX t AVLL t QVWH A0–A7 DATA A16–A23 A8–A15 Figure 73. External Data Memory Write Cycle –73– ADuC834 Variable Core_Clk Min Max Unit 6t – 100 ns CORE t – CORE t – CORE 3t – CORE ...
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... ADuC834 Parameter UART TIMING (Shift Register Mode) t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock QVXH t Input Data Setup to Clock DVXH t Input Data Hold after Clock XHDX t Output Data Hold after Clock XHQX ALE (O) TxD (OUTPUT CLOCK) RxD (OUTPUT DATA) ...
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... MISO MSB IN t DSU REV. A Min 100 100 DAV MSB BITS 6–1 BITS 6–1 t DHD Figure 75. SPI Master Mode Timing (CPHA = 1) –75– ADuC834 Typ Max Unit 630 ns 630 ...
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... ADuC834 Parameter SPI MASTER MODE TIMING (CPHA = 0) t SCLOCK Low Pulsewidth SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge DAV t Data Output Setup before SCLOCK Edge DOSU t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time after SCLOCK Edge ...
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... BITS 6 MSB DSU DHD Figure 77. SPI Slave Mode Timing (CPHA = 1) –77– Typ Max Unit ns 330 ns 330 SFS LSB – 1 LSB IN – ADuC834 Figure ...
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... ADuC834 Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time after SCLOCK Edge ...
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... L 2 Figure 79 Compatible Interface Timing –79– Max Unit µs µs µs ns 0.9 µs µs µs µs 300 ns 300 ACK MSB t DSU F t DHD t RSU SUP S( REPEATED START ADuC834 Figure ...
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... ADuC834 1.03 0.88 0.73 SEATING PLANE VIEW A PIN 1 INDICATOR 1.00 12 MAX 0.90 0.80 0.20 REF SEATING PLANE Revision History Location 4/03—Data Sheet changed from REV REV. A. Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 OUTLINE DIMENSIONS 52-Lead Metric Quad Flat Package [MQFP] (S-52) Dimensions shown in millimeters 14.15 13.90 SQ 2.45 13.65 MAX 39 40 7.80 TOP VIEW REF (PINS DOWN) ...