COP8SBR9 NSC [National Semiconductor], COP8SBR9 Datasheet
COP8SBR9
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COP8SBR9 Summary of contents
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... COP8SBR9/COP8SCR9/COP8SDR9 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout 1.0 General Description The COP8SBR9/SCR9/SDR9 Flash based microcontrollers are highly integrated COP8 ™ Feature core devices, with 32k Flash memory and advanced features including Virtual EE- PROM, High Speed Timers, USART, and Brownout Reset. ...
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Block Diagram 4.0 Ordering Information COP8 SB Family and Feature Set Indicator SB = Low Brownout Voltage SC = High Brownout Voltage Brownout www.national.com Part Numbering Scheme Program Program Memory Memory No. Of ...
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General Description ..................................................................................................................................... 1 2.0 Features ....................................................................................................................................................... 1 3.0 Block Diagram .............................................................................................................................................. 2 4.0 Ordering Information .................................................................................................................................... 2 5.0 Connection Diagrams ................................................................................................................................... 6 6.0 Architectural Overview ............................................................................................................................... 10 6.1 EMI REDUCTION .................................................................................................................................... 10 6.2 IN-SYSTEM PROGRAMMING AND VIRTUAL EEPROM ...
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ITMR Register .................................................................................................................................. 34 12.2 TIMER T1, TIMER T2, AND TIMER T3 ................................................................................................ 35 12.2.1 Timer Operating Speeds .................................................................................................................. 35 12.2.2 Mode 1. Processor Independent PWM Mode ................................................................................. 35 12.2.3 Mode 2. External Event Counter Mode ........................................................................................... 36 12.2.4 ...
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CLOCK MONITOR ................................................................................................................................ 57 16.2 WATCHDOG/CLOCK MONITOR OPERATION .................................................................................... 57 16.3 WATCHDOG AND CLOCK MONITOR SUMMARY .............................................................................. 58 16.4 DETECTION OF ILLEGAL CONDITIONS ............................................................................................ 58 17.0 MICROWIRE/PLUS .................................................................................................................................. 59 17.1 MICROWIRE/PLUS OPERATION ......................................................................................................... 59 17.1.1 MICROWIRE/PLUS Master Mode Operation ...
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Connection Diagrams Top View Plastic Chip Package See NS Package Number V68A Top View LLP Package See NS Package Number LQA44A www.national.com Top View Plastic Chip Package See NS Package Number V44A 10138902 10138940 Top View TSSOP Package See ...
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Connection Diagrams Port Type Alt. Fun L0 I/O MIWU or Low Speed OSC In L1 I/O MIWU or CKX or Low Speed OSC Out L2 I/O MIWU or TDX L3 I/O MIWU or RDX L4 I/O MIWU or T2A ...
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Connection Diagrams Port Type Alt. Fun G7 I CKO I/O E1 I/O E2 I/O E3 I/O E4 I/O E5 I/O E6 I/O ...
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Connection Diagrams Port Type Alt. Fun DGND CKI I RESET operation as WDOUT is controlled by Option Register bit 2. (Continued) TABLE 1. Pinouts for All Packages (Continued) In System Emulation 44-Pin LLP Mode GND 32 ...
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... Architectural Overview 6.1 EMI REDUCTION The COP8SBR9/SCR9/SDR9 devices incorporate circuitry that guards against electromagnetic interference - an in- creasing problem in today’s microcontroller board designs. National’s patented EMI reduction technology offers low EMI clock circuitry, gradual turn-on output drivers (GTOs) and internal Icc smoothing filters, to help circumvent many of the EMI issues influencing embedded control designs. National has achieved 15 dB– ...
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Architectural Overview examples. In many cases, the instruction set can simulta- neously execute as many as three functions with the same single-byte instruction. JID: (Jump Indirect); Single byte instruction decodes exter- nal events and jumps to corresponding service routines ...
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Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin Total Current into V Pin (Source) CC ...
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Electrical Characteristics DC Electrical Characteristics (−40˚C ≤ T Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Output Current Levels D Outputs Source Sink (Note 7) All Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) ...
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Electrical Characteristics AC Electrical Characteristics (−40˚C ≤ T Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Timer 1 Input High Time Timer 1 Input Low Time Timer 2, 3 Input High Time (Note 6) ...
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Electrical Characteristics DC Electrical Characteristics (−40˚C ≤ T Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Dual Clock Mode CKI = 10 MHz, Low Speed OSC = 32 kHz Low Speed Mode Low Speed ...
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Electrical Characteristics AC Electrical Characteristics (−40˚C ≤ T Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Interrupt Input Low Time Timer 1 Input High Time Timer 1 Input Low Time Timer 2, 3 Input ...
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... Pin Descriptions The COP8SBR9/SCR9/SDR9 I/O structure enables design- ers to reconfigure the microcontroller’s I/O functions with a single instruction. Each individual I/O pin can be indepen- dently configured as output pin low, output high, input with high impedance or input with weak pull-up device. A typical example is the use of I/O pins as the keyboard matrix input lines ...
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Pin Descriptions Writing a “1” to bit 6 of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with the alter- nate phase of the SK clock. The G7 configuration bit, if set high, enables the clock start ...
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Pin Descriptions (Continued) FIGURE 6. Emulation Connection 10.0 Functional Description The architecture of the device is a modified Harvard archi- tecture. With the Harvard architecture, the program memory (Flash) is separate from the data store memory (RAM). Both Program ...
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Functional Description (Continued) Figure 7 illustrates how the S register data memory exten- sion is used in extending the lower half of the base address range ( hex) into 256 data segments of 128 bytes each, with ...
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... Example: The following sets a value in the Option Register and User Identification for a COP8SBR9VHA7. The Option Register bit values shown select options: Security disabled, WATCHDOG enabled HALT mode enabled and execution will commence from Flash Memory. .chip 8SBR ...
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Functional Description (Continued) RANDOM after RESET at power-on T2CNTRL: CLEARED T3CNTRL: CLEARED HSTCR: CLEARED ITMR: Cleared except Bit 6 (HSON Accumulator, Timer 1, Timer 2 and Timer 3: RANDOM after RESET WKEN, WKEDG: CLEARED WKPND: RANDOM SP ...
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... CC works correctly. Power supply decoupling is vital even in battery powered systems. There are two optional brownout voltages. The part numbers for the three versions of this device are: COP8SBR9 low voltage range bor (Continued) FIGURE 10. Brownout Reset Operation COP8SCR9, V COP8SDR9, BOR is disabled ...
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Functional Description (Continued) FIGURE 11. Reset Circuit Using Power-On Reset 10.8 OSCILLATOR CIRCUITS The device has two crystal oscillators to facilitate low power operation while maintaining throughput when required. Fur- ther information on the use of the two oscillators ...
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Functional Description High Speed Oscillator 10138915 10.9 CONTROL REGISTERS 10.9.1 CNTRL Register (Address X'00EE) T1C3 T1C2 T1C1 T1C0 MSEL Bit 7 The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: T1C3 Timer T1 mode control bit T1C2 ...
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Functional Description (Continued) 10.9.5 T3CNTRL Register (Address X'00B6) T3C3 T3C2 T3C1 T3C0 T3PNDA Bit 7 The T3CNTRL register contains the following bits: T3C3 Timer T3 mode control bit T3C2 Timer T3 mode control bit T3C1 Timer T3 mode control ...
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In-System Programming 11.1 INTRODUCTION This device provides the capability to program the program memory while installed in an application board. This feature is called In System Programming (ISP). It provides a means of ISP by using the MICROWIRE/PLUS, or ...
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In-System Programming (Continued) 11.3.2 ISP Read Data Register The Read Data Register (ISPRD) contains the value read back from a read operation. This register can be accessed from either flash program memory or Boot ROM. This regis- ter is ...
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In-System Programming (Continued) 11.4 MANEUVERING BACK AND FORTH BETWEEN FLASH MEMORY AND BOOT ROM When using ISP, at some point, it will be necessary to maneuver between the flash program memory and the Boot ROM, even when using customized ...
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In-System Programming (Continued) 11.6 RETURN TO FLASH MEMORY WITHOUT HARDWARE RESET After programming the entire program memory, including options necessary to exit the Boot ROM and return to the flash program memory for program execution. Upon receipt ...
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In-System Programming (Continued) • Copy a block of data from RAM into flash program memory. • Copy a block of data from program flash memory to RAM. The following table lists the User ISP/Virtual E required parameters and return ...
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In-System Programming TABLE 11. User ISP/Virtual E Command/ Command Function Label Entry Point uwisp MICROWIRE/ 0x00 PLUS ISP Start Register Name ISPADHI High byte of Flash Memory Address ISPADLO Low byte of Flash Memory Address ISPWR The user must ...
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In-System Programming (Continued) TABLE 13. Typical Flash Memory Endurance Low End of Operating Temp Range Erase −40˚C −20˚C 0˚C Time 1 ms 60k 60k 60k 2 ms 60k 60k 60k 3 ms 60k 60k 60k Low End of Operating ...
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Timers The device contains a very versatile set of timers (T0, T1, T2 and T3). Timers T1, T2 and T3 and associated autoreload/ capture registers power up containing random data. 12.1 TIMER T0 (IDLE TIMER) The device supports applications ...
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Timers (Continued) Note: Documentation for previous COP8 devices, which in- cluded the Programmable Idle Timer, recommended the user write zero to the high order bits of the ITMR Register. If existing programs are updated to use this device, writing ...
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Timers (Continued) 12.2.3 Mode 2. External Event Counter Mode This mode is quite similar to the processor independent PWM mode described above. The main difference is that the timer, Tx, is clocked by the input signal from the TxA ...
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Timers (Continued) TxENB Timer Interrupt Enable Flag 1 = Timer Interrupt Enabled 0 = Timer Interrupt Disabled The timer mode control bits (TxC3, TxC2 and TxC1) are detailed in Table 15, Timer Operating Modes. When the high speed timers ...
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Power Saving Features 13.1 POWER SAVE MODE CONTROL REGISTER The ITMR control register allows for navigation between the three different modes of operation also used for the Idle Timer. The register bit assignments are shown below. This ...
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Power Saving Features (Continued) 13.2 OSCILLATOR STABILIZATION Both the high speed oscillator and low speed oscillator have a startup delay associated with them. When switching be- tween the modes, the software must ensure that the appro- priate oscillator is ...
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Power Saving Features 13.3.2 High Speed Idle Mode In the IDLE mode, program execution stops and power consumption is reduced to a very low level as with the HALT mode. However, the high speed oscillator, IDLE Timer (Timer T0), ...
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Power Saving Features (Continued) 3. Software clears the CCKSEL bit to 0. 13.4.1 Dual Clock HALT Mode The fully static architecture of this device allows the state of the microcontroller to be frozen. This is accomplished by stopping the ...
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Power Saving Features (Continued) IDLE Timer which is associated with the selected window. Another method is to poll the state of the IDLE Timer pending bit T0PND, which is set on the same occurrence. The Idle Timer interrupt is ...
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Power Saving Features (Continued) interrupt is enabled, the interrupt is serviced before execu- tion of the main program resumes. (However, the instruction which was started as the part entered the IDLE mode is completed before the interrupt is serviced. ...
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Power Saving Features (Continued) associated WKEN bit should be reset, followed by the edge select change in WKEDG. Next, the associated WKPND bit should be cleared, followed by the associated WKEN bit being re-enabled. An example may serve to ...
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USART (Continued) 14.1 USART CONTROL AND STATUS REGISTERS The operation of the USART is programmed through three registers: ENU, ENUR and ENUI. 14.2 DESCRIPTION OF USART REGISTER BITS ENU — USART CONTROL AND STATUS REGISTER (Ad- dress at 0BA) ...
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USART (Continued) Read/Write, cleared on reset. CHL1 = 0, CHL0 = 0 The frame contains eight data bits. CHL1 = 0, CHL0 = 1 The frame contains seven data bits. CHL1 = 1, CHL0 = 0 The frame contains ...
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USART (Continued) 14.4.1 Asynchronous Mode This mode is selected by resetting the SSEL (in the ENUI register) bit to zero. The input frequency to the USART is 16 times the baud rate. The TSFT and TBUF registers double-buffer data ...
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USART (Continued) 14.6 USART INTERRUPTS The USART is capable of generating interrupts. Interrupts are generated on Receive Buffer Full and Transmit Buffer Empty. Both interrupts have individual interrupt vectors. Two bytes of program memory space are reserved for each ...
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USART (Continued) many ways to calculate the two divisor factors, but one particularly effective method would be to achieve a 1.8432 MHz frequency coming out of the first stage. The 1.8432 MHz prescaler output is then used to drive ...
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USART (Continued) Using the above equation can be calculated first 2)/(16 x 19200) = 32.552 Now 32.552 is divided by each Prescaler Factor (Table 18) to obtain ...
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Interrupts 15.1 INTRODUCTION The device supports fourteen vectored interrupts. Interrupt sources include Timer 1, Timer 2, Timer 3, Timer T0, Port L Wake-up, Software Trap, MICROWIRE/PLUS, USART and External Input. All interrupts force a branch to location 00FF Hex ...
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Interrupts (Continued) enabled; if the pending bit is already set, it will immediately trigger an interrupt. A maskable interrupt is active if its asso- ciated enable and pending bits are set. An interrupt is an asychronous event which may ...
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Interrupts (Continued) The default VIS interrupt vector can be useful for applica- tions in which time critical interrupts can occur during the servicing of another interrupt. Rather than restoring the pro- gram context ( etc.) and executing ...
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Interrupts (Continued) 15.4 NON-MASKABLE INTERRUPT 15.4.1 Pending Flag There is a pending flag bit associated with the non-maskable Software Trap interrupt, called STPND. This pending flag is not memory-mapped and cannot be accessed directly by the software. The pending ...
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Interrupts (Continued) STPND flag will have the wrong state. This will allow maskable interrupts to be acknowledged during the servicing of the first Software Trap. To avoid problems such as this, the user program should contain the Software Trap ...
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Interrupts (Continued) 15.4.2.1 Programming Example: External Interrupt PSW =00EF CNTRL =00EE RBIT 0,PORTGC RBIT 0,PORTGD SBIT IEDG, CNTRL SBIT GIE, PSW SBIT EXEN, PSW WAIT: JP WAIT . . . .=0FF VIS . . . .=01FA .ADDRW SERVICE . ...
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WATCHDOG/Clock Monitor The devices contain a user selectable WATCHDOG and clock monitor. The following section is applicable only if the WATCHDOG feature has been selected in the Option regis- ter. The WATCHDOG is designed to detect the user program ...
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WATCHDOG/Clock Monitor (Continued) trigger threshold. After this delay, the device will stop forcing the WDOUT output low. The WATCHDOG service window will restart when the WDOUT pin goes high. A WATCHDOG service while the WDOUT signal is active will ...
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WATCHDOG/Clock Monitor (Continued) turn will cause the program to return to address 7FFF Hex. The Option Register is located at this location and, when accessed by an instruction fetch, will respond with an INTR instruction (all 0’s) to generate ...
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MICROWIRE/PLUS 17.1.2.1 Alternate SK Phase Operation and SK Idle Polarity The device allows either the normal SK clock or an alternate phase SK clock to shift data in and out of the SIO register. In both the modes the ...
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MICROWIRE/PLUS FIGURE 31. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being Low FIGURE 32. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being High FIGURE 33. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate ...
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Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. Address Contents S/ADD REG 0000 to 006F On-Chip RAM bytes (112 bytes) 0070 to 007F Unused RAM Address Space (Reads As ...
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Memory Map (Continued) Address Contents S/ADD REG xxE7 Timer T1 Autoload Register T1RB Upper Byte xxE8 ICNTRL Register xxE9 MICROWIRE/PLUS Shift Register xxEA Timer T1 Lower Byte xxEB Timer T1 Upper Byte xxEC Timer T1 Autoload Register T1RA Lower ...
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Instruction Set 19.1 INTRODUCTION This section defines the instruction set of the COP8 Family members. It contains information about the instruction set features, addressing modes and types. 19.2 INSTRUCTION FEATURES The strength of the instruction set is based on ...
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Instruction Set (Continued) Reg/Data Contents Memory Before Accumulator XX Hex Immediate Short. This is a special case of an immediate instruction. In the “Load B immediate” instruction, the 4-bit immediate value in the instruction is loaded into the lower ...
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Instruction Set (Continued) associated with the interrupt is transferred from adjacent addresses in program memory into the Program Counter in order to jump to the associated interrupt service routine. 19.4 INSTRUCTION TYPES The instruction set contains a wide variety ...
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Instruction Set (Continued) 19.5 REGISTER AND SYMBOL DEFINITION The following abbreviations represent the nomenclature used in the instruction description and the COP8 cross- assembler. Registers A 8-Bit Accumulator Register B 8-Bit Address Register X 8-Bit Address Register S 8-Bit ...
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Instruction Set (Continued) INC A INCrement A DEC A DECrement A LAID Load A InDirect from ROM DCOR A Decimal CORrect A RRC A Rotate A Right thru C RLC A Rotate A Left thru C SWAP A SWAP ...
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Instruction Set (Continued) 19.7 INSTRUCTION EXECUTION TIME Most instructions are single byte (with immediate addressing mode instructions taking two bytes). Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be ...
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Nibble Lower 70 ...
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... KANDA’s Flash COP8ISP ISP Programmer www.kanda.com Softec Flash ISP www.softecmicro.com Programmer Development COP8CBR9/CCR9/CDR9 Devices COP8CBE9/CCE9 COP8SBR9/SCR9/SDR9 COP8SBE9/SCE9 COP8AME9/ANE9 < *Cost: Free; VL= $100; L=$100-$300; M=$300-$1k; H=$1k-$3k; VH=$3k-$5k www.national.com (Continued) L Includes 110v/220v p/s, target cable with 2x7 connector pin COP8CDR9 Null Target, manuals and software on CD. ...
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... WCOP8 IDE and Emulator Debugger, with Assembler/ Linker/ CD-ROM Simulators/ Library Manager/ Compiler Demos/ Flash ISP and NiceMon Debugger Utilities/ Example Code/ etc. Includes all COP8 datasheets and documentation. Included with most tools from National. Unis Processor Processor Expert( from Unis Corporation - COP8 Code Generation and Simulation Expert tool with Graphical and Traditional user interfaces ...
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Development Support Hardware Tools for: Real-time Emulation; Target Hardware Debug; Target Design Test. Product COP8Flash COP8 In-Circuit Emulator for Flash Families. Windows based development and Emulators - real-time in-circuit emulation tool, with trace (EM=None; DM/IM=32k), s/w COP8-EMFlash breakpoints (DM=16, ...
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Development Support Vendor Home Office KANDA Systems Unit 17 -18 LTD. Glanyrafon Enterprise Park, Aberystwyth, Ceredigion, SY23 3JQ, UK Tel: +44 1970 621041 Fax: +44 1970 621040 K and K Kaergaardsvej 42 DK-8355 Development ApS Solbjerg Denmark Fax: +45-8692-8500 ...
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Revision History Date Section October 2000 March 2001 Throughout General Description Ordering Information Electrical Specifications Functional Description In-System Programming Clarified use of high voltage on G6 pin to force execution from Boot ROM. USART Development Support September 2001 General ...
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... Physical Dimensions Order Number COP8SBR9HLQ8 or COP8SCR9HLQ7 or COP8SDR9HLQ7 inches (millimeters) unless otherwise noted LLP Package (LQA) or COP8SCR9HLQ8 or COP8SDR9HLQ8 NS Package Number LQA44A 77 www.national.com ...
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... Physical Dimensions Order Number COP8SBR9IMT8 or COP8SCR9IMT7 or COP8SDR9IMT7 Order Number COP8SBR9KMT8 or COP8SCR9KMT7 or COP8SCR9KMT8 www.national.com inches (millimeters) unless otherwise noted (Continued) TSSOP Package (MTD) or COP8SCR9IMT8 or COP8SDR9IMTA8 NS Package Number MTD48 TSSOP Package (MTD) or COP8CSDR9KMT7 or COP8SDR9KMTA8 NS Package Number MTD56 78 ...
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... Physical Dimensions Order Number COP8SBR9HVA8 or COP8SCR9HVA7 or COP8SCR9HVA8 Order Number COP8SBR9LVA8 or COP8SCR9LVA7 or COP8SCR9LVA8 inches (millimeters) unless otherwise noted (Continued) Plastic Leaded Chip Carrier (VA) or COP8SDR9HVA7 or COP8SDR9HVA8 NS Package Number V44A Plastic Leaded Chip Carrier (VA) or COP8SDR9LVA7 or COP8SDR9LVA8 NS Package Number V68A 79 www.national.com ...
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LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support ...