DS90C383 National Semiconductor, DS90C383 Datasheet

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DS90C383

Manufacturer Part Number
DS90C383
Description
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz/ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
Manufacturer
National Semiconductor
Datasheet

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© 1999 National Semiconductor Corporation
DS90C383/DS90CF384
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel
Display (FPD) Link— 65 MHz, +3.3V LVDS Receiver
24-Bit Flat Panel Display (FPD) Link— 65 MHz
General Description
The DS90C383 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. The DS90CF384 receiver converts the LVDS
data streams back into 28 bits of CMOS/TTL data. At a trans-
mit clock frequency of 65 MHz, 24 bits of RGB data and 3
bits of LCD timing and control data (FPLINE, FPFRAME,
DRDY) are transmitted at a rate of 455 Mbps per LVDS data
channel. Using a 65 MHz clock, the data throughputs is 227
Mbytes/sec. The transmitter is offered with programmable
edge data strobes for convenient interface with a variety of
graphics controllers. The transmitter can be programmed for
Rising edge strobe or Falling edge strobe through a dedi-
cated pin. A Rising edge transmitter will inter-operate with a
Falling edge receiver (DS90CF384) without any translation
logic. The DS90CF384 is also offered in 64 ball, 0.8mm fine
pitch ball grid array(FBGA) package which provides a 44 %
reduction in PCB footprint (available Q3, 1999).
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Block Diagrams
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
DS012887
Application
Features
n 20 to 65 MHz shift clock support
n Programmable transmitter (DS90C383) strobe select
n Single 3.3V supply
n Chipset (Tx + Rx) power consumption
n Power-down mode (
n Single pixel per clock XGA (1024x768) ready
n Supports VGA, SVGA, XGA and higher addressability.
n Up to 227 Megabytes/sec bandwidth
n Up to 1.8 Gbps throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 56-lead TSSOP package.
n DS90CF384 also available in 64 ball, 0.8mm fine pitch
n Falling edge data strobe Receiver
n Compatible with TIA/EIA-644 LVDS standard
n ESD rating
n Operating Temperature: −40˚C to +85˚C
(Rising or Falling edge strobe)
ball grid array(FBGA) package
>
7 kV
<
0.5 mW total)
<
September 1999
DS012887-2
250 mW (typ)
www.national.com

Related parts for DS90C383

DS90C383 Summary of contents

Page 1

... Display (FPD) Link— 65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link— 65 MHz General Description The DS90C383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in par- allel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted ...

Page 2

... Block Diagrams (Continued) Order Number DS90CF384MTD or DS90CF384SLC www.national.com DS90C383 Order Number DS90C383MTD See NS Package Number MTD56 DS90CF384 See NS Package Number MTD56 or SLC64A 2 DS012887-1 DS012887-24 ...

Page 3

... V Differential Input High Threshold TH V Differential Input Low Threshold TL I Input Current IN TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current Worst Case (Note 1) DS90C383MTD DS90CF384MTD Maximum Package Power Dissipation Capacity 25˚C SLC64A Package: DS90CF384SLC −0.3V to +4V Package Derating: + 0.3V) CC DS90CF384SLC + 0.3V 0.3V) CC ESD Rating + 0 ...

Page 4

Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter TRANSMITTER SUPPLY CURRENT ICCTG Transmitter Supply Current 16 Grayscale ICCTZ Transmitter Supply Current Power Down RECEIVER SUPPLY CURRENT ICCRW Receiver Supply Current Worst Case ICCRG Receiver ...

Page 5

Receiver Switching Characteristics Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified Symbol CLHT CMOS/TTL Low-to-High Transition Time (Figure 4 ) CMOS/TTL High-to-Low Transition Time (Figure 4 ) CHLT RSPos0 Receiver Input Strobe Position for Bit 0 ...

Page 6

... Note 8: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Note 9: Recommended pin to signal mapping. Customer may choose to define differently. FIGURE 3. DS90C383 (Transmitter) LVDS Output Load and Transition Times FIGURE 4. DS90CF384 (Receiver) CMOS/TTL Output Load and Transition Times www.national.com ...

Page 7

... TCCS measured between earliest and latest LVDS edges. TxCLK Differential Low High Edge FIGURE 6. DS90C383 (Transmitter) Channel-to-Channel Skew FIGURE 7. DS90C383 (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) FIGURE 8. DS90CF384 (Receiver) Setup/Hold and High/Low Times DS012887-7 DS012887-8 DS012887-9 ...

Page 8

... AC Timing Diagrams (Continued) FIGURE 9. DS90C383 (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe) FIGURE 10. DS90CF384 (Receiver) Clock In to Clock Out Delay FIGURE 11. DS90C383 (Transmitter) Phase Lock Loop Set Time FIGURE 12. DS90CF384 (Receiver) Phase Lock Loop Set Time www.national.com DS012887-11 DS012887-12 ...

Page 9

AC Timing Diagrams (Continued) FIGURE 13. Seven Bits of LVDS in Once Clock Cycle FIGURE 14. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs FIGURE 15. Transmitter Power Down Delay DS012887-17 9 DS012887-15 DS012887-16 www.national.com ...

Page 10

AC Timing Diagrams (Continued) FIGURE 17. Transmitter LVDS Output Pulse Position Measurement www.national.com FIGURE 16. Receiver Power Down Delay 10 DS012887-18 DS012887-26 ...

Page 11

AC Timing Diagrams (Continued) FIGURE 18. Receiver LVDS Input Strobe Position 11 DS012887-25 www.national.com ...

Page 12

... Cable Skew — typically 10 ps–40 ps per foot, media dependent Note 10: Cycle-to-cycle jitter is less than 250 MHZ Note 11: ISI is dependent on interconnect length; may be zero FIGURE 19. Receiver LVDS Input Skew Margin DS90C383 Pin Description — FPD Link Transmitter Pin Name I/O No. ...

Page 13

DS90CF384 MTD56 package Pin Description — FPD Link Receiver Pin Name I/O No. RxIN Positive LVDS differentiaI data inputs. RxIN− Negative LVDS differential data inputs. RxOUT O 28 TTL level data outputs. This includes: 8 Red, ...

Page 14

... OR left unconnected. When not connected (left open) and internal pull-down resistor ties pin 17 to ground, thus configuring the trans- mitter with a falling edge strobe. 3. The DS90C383 transmitter input and control inputs ac- cept 3.3V TTL/CMOS levels. They are not 5V tolerant. www.national.com Description ...

Page 15

... Pin Diagrams DS90C383MTD DS012887-22 Pin R_FB R_FB DS90CF384MTD TABLE 1. Programmable Transmitter Condition Strobe Status R_FB = V Rising edge strobe CC R_FB = GND Falling edge strobe 15 DS012887-23 www.national.com ...

Page 16

DS90CF384 64 ball, FBGA package pin definition — FPD Link Receiver By Pin Pin Pin Name A1 RxOUT17 A2 VCC A3 RxOUT15 A4 GND A5 RxOUT12 A6 RxOUT8 A7 RxOUT7 A8 RxOUT6 B1 GND RxOUT16 B4 RxOUT11 ...

Page 17

DS90CF384 64 ball, FBGA package pin definition — FPD Link Receiver (Continued) By Pin G1 RxOUT25 LVDS GND G4 RxIN1+ G5 RxIN2- G6 RxIN3- G7 LVDS GND G8 PLL GND H1 RxOUT27 H2 RxIN0- H3 RxIN0+ H4 ...

Page 18

... Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90C383MTD, DS90CF384MTD www.national.com Dimensions show in millimeters NS Package Number MTD56 18 ...

Page 19

... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...

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