IDT7006S Integrated Device Technology, IDT7006S Datasheet
IDT7006S
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IDT7006S Summary of contents
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... True Dual-Ported memory cells which allow simulta- neous access of the same memory location • High-speed access — Military: 20/25/35/55/70ns (max.) — Commercial: 15/17/20/25/35/55ns (max.) • Low-power operation — IDT7006S Active: 750mW (typ.) Standby: 5mW (typ.) — IDT7006L Active: 750mW (typ.) Standby: 1mW (typ.) • ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM PIN CONFIGURATIONS (CONT' 11L N SEM I I I/O A INDEX NOTES: 1. All V pins must be connected to power supply. ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL (1) Inputs Outputs SEM SEM SEM SEM SEM DATA NOTE — not equal to A — ...
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... MIL. S (5) > 0.2V CC SEM = > V -0.2V — 0.2V or 100 COM (3) = 120mA (typ.). CC DC 6.07 MILITARY AND COMMERCIAL TEMPERATURE RANGES (V = 5.0V 10%) CC IDT7006S IDT7006L Min. Max. Min. — 10 — CC — 10 — — 0.4 — 2.4 — 2.4 ( 5.0V 10%) CC 7006X17 7006X20 Com'l. Only (2) (2) Max. ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter I Dynamic Operating CC Current (Both Ports Active) I Standby Current SB1 (Both Ports — TTL Level Inputs) I Standby Current SB2 (One Port — TTL ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Parameter Symbol READ CYCLE t Read Cycle Time ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM WAVEFORM OF READ CYCLES ADDRESS DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, 2. Timing depends on which signal is de-asserted first delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BDD BUSY has no relation to valid output data ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter WRITE CYCLE t Write Cycle Time WC t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW (3) t Address Set-up Time AS t Write Pulse Width ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM TIMING WAVEFORM OF WRITE CYCLE NO ADDRESS OE (9) CE SEM or ( DATA (4) OUT DATA IN TIMING WAVEFORM OF WRITE CYCLE NO. 2, ADDRESS CE SEM ( DATA IN NOTES must be High during all address transitions. ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE VALID ADDRESS t AW SEM I Write Cycle NOTES for the duration of the above timing (both write and read cycle "DATA VALID" ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter BUSY TIMING ( BUSY t Access Time from Address Match BAA BUSY t Disable Time from Address Not Matched BDA BUSY t Access Time from Chip Enable Low ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND ADDR "A" "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins. t ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING (1) ( ADDR "A" ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM WAVEFORM OF INTERRUPT TIMING ADDR "A" ( "A" "A" t "B" INT ADDR "B" ( "B" OE "B" t INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM TRUTH TABLE II — ADDRESS BUSY ARBITRATION Inputs Outputs 13L ( 13R BUSY BUSY BUSY BUSY BUSY MATCH MATCH MATCH L L (2) MATCH NOTES: 1 ...
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... These systems can benefit from a performance increase offered by the IDT7006s hardware semaphores, which pro- vide a lockout mechanism without requiring complex pro- gramming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove major advantage in very high-speed systems. HOW THE SEMAPHORE FLAGS WORK The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. USING SEMAPHORES— ...
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... IDT7006S/L HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM ORDERING INFORMATION IDT XXXXX A 999 Device Power Speed Type A A Package Process/ Temperature Range Blank 7006 6.07 MILITARY AND COMMERCIAL TEMPERATURE RANGES Commercial ( +70 C) Military (– +125 C) ...