IDT70V261 Integrated Device Technology, IDT70V261 Datasheet

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IDT70V261

Manufacturer Part Number
IDT70V261
Description
16k X 16 3.3v Dual-port Ram W/int
Manufacturer
Integrated Device Technology
Datasheet

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Features
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
©2008 Integrated Device Technology, Inc.
Functional Block Diagram
I/O
I/O
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 25/35/55ns (max.)
– Industrial: 25ns (max.)
Low-power operation
– IDT70V261S
– IDT70V261L
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
8L
0L
BUSY
-I/O
Active: 300mW (typ.)
Standby: 3.3mW (typ.)
Active: 300mW (typ.)
Standby: 660 µ W (typ.)
-I/O
SEM
R/W
A
INT
UB
CE
OE
LB
A
15L
13L
7L
0L
L
L
L
L
L
L
L
L
(1,2)
(2)
Decoder
Address
R/W
OE
CE
L
L
L
14
HIGH-SPEED 3.3V
16K x 16 DUAL-PORT
STATIC RAM
Control
I/O
ARBITRATION
SEMAPHORE
INTERRUPT
MEMORY
ARRAY
LOGIC
M/S
1
IDT70V261 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
M/S = V
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP, Thin Quad Plastic Flatpack
Industrial temperature range (-40°C to +85°C) is available
for selected speed
Green parts available, see ordering information
Control
IH
IL
I/O
for BUSY input on Slave
for BUSY output flag on Master
14
Decoder
Address
CE
OE
R/W
R
R
R
FEBRUARY 2008
IDT70V261S/L
3040 drw 01
I/O
R/W
UB
I/O
BUSY
A
A
SEM
INT
OE
LB
CE
13R
0R
8R
R
0R
DSC-3040/9
R
R
R
R
R
R
(2)
-I/O
-I/O
R
(1,2)
15R
7R

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IDT70V261 Summary of contents

Page 1

... BUSY and INT outputs are non-tri-stated push-pull. ©2008 Integrated Device Technology, Inc. HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM IDT70V261 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device for BUSY output flag on Master M ...

Page 2

... IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Description The IDT70V261 is a high-speed 16K x 16 Dual-Port Static RAM. The IDT70V261 is designed to be used as a stand-alone 256K-bit Dual-Port RAM combination MASTER/SLAVE Dual-Port RAM for 32-bit-or- more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in full- speed, error-free operation without the need for additional discrete logic ...

Page 3

... IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Truth Table I: Non-Contention Read/Write Control (1) Inputs R NOTE: ≠ — A — 13L ...

Page 4

... IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Absolute Maximum Ratings Symbol Rating (2) V Terminal Voltage TERM with Respect to GND Temperature T BIAS Under Bias Storage T STG Temperature I DC Output OUT Current NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 5

... IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter Dynamic Operating CC SEM = V Current (Both Ports Active MAX Standby Current SB1 R SEM = SEM (Both Ports - TTL R Level Inputs) ...

Page 6

... IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load Timing of Power-Up Power-Down Electrical Characteristics Over the Operating Temperature and Supply Voltage Range ...

Page 7

... IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Waveform of Read Cycles ADDR CE OE UB, LB R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB. delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no 3 ...

Page 8

... IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Timing Waveform of Write Cycle No. 1, R/W Controlled Timing ADDRESS OE ( SEM ( SEM ( R/W (4) DATA OUT DATA IN Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing ADDRESS ( SEM ( ( ...

Page 9

... IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM I R/W OE NOTES & for the duration of the above timing (both write and read cycle). ...

Page 10

... IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (M BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not Match t BDA BUSY Access Time from Chip Enable Low ...

Page 11

... IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Timing Waveform of Write with R/W "A" BUSY "B" R/W "B" NOTES: must be met for both BUSY input (SLAVE) and output (MASTER BUSY is asserted on port "B" blocking R/W "B" ...

Page 12

... IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS t Interrupt Reset Time INR NOTES: 1. 'X' in part number indicates power rating (S or L). ...

Page 13

... Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V261. 2. There are eight semaphore flags written to via I SEM = V to access the semaphore ...

Page 14

... V per Truth master use the BUSY signal as a write inhibit signal. Thus on the IDT70V261 SRAM the BUSY pin is an output if the part is used as a master (M/S pin = slave (M/S pin = two or more master parts were used when expanding in width, a ...

Page 15

... The eight semaphore flags reside within the IDT70V261 in a separate memory space from the Dual-Port SRAM. This address space is accessed by placing a LOW input on the SEM pin (which acts ...

Page 16

... Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their applica- tion as resource markers for the IDT70V261’s Dual-Port RAM. Say the 16K x 16 RAM was to be divided into two blocks which were to be dedicated at any one time to servicing either the left or right port. ...

Page 17

... IDT70V261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Ordering Information IDT XXXXX A A 999 Device Power Speed Type NOTES: 1. For other speeds, packages and powers contact your sales office. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. ...

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