IDT72413 Integrated Device Technology, IDT72413 Datasheet

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IDT72413

Manufacturer Part Number
IDT72413
Description
Cmos Parallel 64 X 5-bit Fifo With Flags
Manufacturer
Integrated Device Technology
Datasheet

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FUNCTIONAL BLOCK DIAGRAM
 2003
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.
COMMERCIAL TEMPERATURE RANGE
FEATURES:
• First-ln/First-Out Dual-Port memory—45MHz
• 64 x 5 organization
• Low-power consumption
• RAM-based internal structure allows for fast fall-through time
• Asynchronous and simultaneous read and write
• Expandable by bit width
• Cascadable by word depth
• Half-Full and Almost-Full/Empty status flags
• High-speed data communications applications
• Bidirectional and rate buffer applications
• High-performance CMOS technology
• Available in plastic DIP and SOIC
• Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
— Active: 200mW (typical)
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MASTER
DATA
READY
RESET
INPUT
SHIFT
(D
0-4
IN
IN
)
(MR)
(IR)
(SI)
CMOS PARALLEL FIFO WITH FLAGS 64 x 5
CONTROL
STAGE
LOGIC
INPUT
INPUT
FIFO
REGISTER
CONTROL
CONTROL
MEMORY
ARRAY
LOGIC
LOGIC
64 x 5
FLAG
1
DESCRIPTION:
and empties data on a first-in-first-out basis. It is expandable in bit width. All speed
versions are cascad-able in depth.
in memory. The Almost-Full/Empty Flag is active when there are 56 or more
words in memory or when there are 8 or less words in memory.
at a shift rate of 45MHz. This makes it ideal for use in high-speed data buffering
applications. This FIFO can be used as a rate buffer, between two digital systems
of varying data rates, in high-speed tape drivers, hard disk controllers, data
communications controllers anD graphics controllers.
This process maintains the speed and high output drive capability of TTL circuits
in low-power CMOS.
The IDT72413 is a 64 x 5, high-speed First-In/First-Out (FIFO) that loads
The FIFO has a Half-Full Flag, which signals when it has 32 or more words
This device is pin and functionally compatible to the MMI67413. It operates
The IDT72413 is fabricated using IDTs high-performance CMOS process.
OUPUT ENABLE
CONTROL
HALF-FULL (HF)
ALMOST-FULL/
EMPTY (AF/E)
OUTPUT
OUTPUT
STAGE
LOGIC
FIFO
(OE)
(SO)
(OR)
2748 drw 01
DATA
(Q
OUPUT
READY
SHIFT
OUT
0-4
)
OUT
JULY 2003
IDT72413
DSC-2748/9

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IDT72413 Summary of contents

Page 1

... Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. CMOS PARALLEL FIFO WITH FLAGS DESCRIPTION: The IDT72413 high-speed First-In/First-Out (FIFO) that loads and empties data on a first-in-first-out basis expandable in bit width. All speed versions are cascad-able in depth. ...

Page 2

... IDT72413 CMOS PARALLEL FIFO WITH FLAGS PIN CONFIGURATION GND 10 PLASTIC DIP (P20-1, ORDER CODE: P) SOIC (SO20-2, ORDER CODE: SO) TOP VIEW CAPACITANCE (T = +25° 1.0MHz) A Symbol Parameter Conditions C Input Capacitance ...

Page 3

... IDT72413 CMOS PARALLEL FIFO WITH FLAGS OPERATING CONDITIONS (Commercial 5.0V ± 10 0°C to +70° Symbol Parameter (1) t Shift in HIGH Time SIH (1) t Shift in LOW TIme SIL t Input Data Set-up IDS t Input Data Hold Time IDH (1) t Shift Out HIGH Time ...

Page 4

... Output Reference Levels Output Load FUNCTIONAL DESCRIPTION: The IDT72413 FIFO is designed using a dual-port RAM architecture as opposed to the traditional shift register approach. This FIFO architecture has a write pointer, a read pointer and control logic, which allow simultaneous read and write operations. The write pointer is incremented by the falling edge of the Shift In (Sl) control ...

Page 5

... Output Enable is used to enable the FIFO outputs onto a bus active LOW. ALMOST-FULL/EMPTY FLAG (AF/E) Almost-Full/Empty Flag signals when the FIFO is 7/8 full (56 or more words) or 1/8 from empty (8 or less words). OUTPUTS: DATA OUTPUT (Q Data output lines, three-state. The IDT72413 has a 5-bit output. 1 SIL t IRL Figure 2 ...

Page 6

... IDT72413 CMOS PARALLEL FIFO WITH FLAGS ( (1) INPUT DATA NOTES: 1. FIFO is initially full pulse is applied held HIGH soon as IR becomes HIGH the Input Data is loaded into the FIFO. 5. The write pointer is incremented. SI should not go LOW until (t Figure 4 ...

Page 7

... IDT72413 CMOS PARALLEL FIFO WITH FLAGS (1) NOTE: 1. FIFO initailly empty (1) MRIRL IR t (1) MRORL MRQ DATA OUTPUTS AF/E NOTE: 1. FIFO is partially full. t SOH SO (1) AF/E SI NOTE: 1. FIFO contains 9 words (one more than Almost-Empty Figure 7. t and t ...

Page 8

... IDT72413 CMOS PARALLEL FIFO WITH FLAGS SIH SI t HFH ( NOTE: 1. FIFO contains 55 words (one short of Almost-Full). t SIH SI t HFH ( NOTE: 1. FIFO contains 31 words (one short of Half-Full). WAVEFORM 1 WAVEFORM 2 NOTES: 1. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. ...

Page 9

... FIFOs are expandable in width. However, in forming wider words two external gates are required to generate composite Input and Output Ready flags. This requirement is due to the different fall-through times of the FIFOs. SYSTEM 1 ENBL SI INTERRUPT NOTE: 1. Cascading the FIFOs in word width is done by ANDing the IR and OR as shown in Figure 13. Figure 14. Application for IDT72413 for Two Asynchronous Systems ...

Page 10

SHIFT IN SI INPUT READY DATA NOTE: 1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing ...

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