IDT72V3656 IDT [Integrated Device Technology], IDT72V3656 Datasheet

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... Offset Registers Mode FIFO2 Status Flag Logic Read Write Pointer Pointer RAM ARRAY 36 36 2,048 x 36 4,096 x 36 8,192 x 36 Mail 2 Register 1 TM WITH BUS-MATCHING IDT72V3656 IDT72V3666 IDT72V3676 MBF1 CLKB Port-B RENB Control CSB Logic MBB SIZEB EFB/ORB AEB Common ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 DESCRIPTION The IDT72V3656/72V3666/72V3676 are pin and functionally compatible versions of the IDT723626/723636/723646, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are a monolithic, ...

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... Two or more FIFOs may be used in parallel to create wider data paths. Such a width expansion requires no additional, external components. Further- more, two IDT72V3656/72V3666/72V3676 FIFOs can be combined with unidirectional FIFOs capable of First Word Fall Through timing (i.e. the SuperSync FIFO family) to form a depth expansion. ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 PIN DESCRIPTIONS Symbol Name I/O A0-A35 Port A Data I/O AEA Port A Almost- O Empty Flag AEB Port B Almost- O Empty Flag AFA Port A Almost- O Full Flag AFC ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O FS0/SD Flag Offset Select 0/ I FS1/SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During Master Reset, Serial Data FS1/SEN and FS0/SD, together with FS2, select the flag offset programming method ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O SIZEB (1) Port B I SIZEB determines the bus width of Port B. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin Bus Size Select selects word (18-bit) bus size ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted) Symbol V Supply Voltage Range CC (2) V Input Voltage Range I (2) V Output Voltage Range ...

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... WITH BUS MATCHING 2,048 4,096 and 8,192 DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3656/72V3666/72V3676 with CLKA, CC(f) CLKB and CLKC set to f ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (For 10ns speed grade only: Vcc = 3.3V 0.15V ± Symbol Parameter f Clock Frequency, CLKA, CLKB, or CLKC ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE 30PF (For 10ns speed grade only: Vcc = 3.3V 0.15V ± Symbol Parameter t Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B17 A Propagation Delay Time, CLKA↑ ...

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... After power up, a Master Reset operation must be performed by providing a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, the FIFO1 memory of the IDT72V3656/72V3666/72V3676 undergoes a complete reset by taking its associated Master Reset (MRS1) input LOW for at least four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The ...

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... The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers range from 1 to 2,044 for the IDT72V3656 4,092 for the IDT72V3666; and 1 to 8,188 for the IDT72V3676. After all the Offset registers are programmed from Port A, the Port C Full/Input Ready flag (FFC/IRC) is set HIGH, and both FIFOs begin normal operation ...

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... IDT72V3676, respectively. The four registers are written in the order Y1, X1, Y2 and finally, X2. The first-bit write stores the most significant bit of the Y1 register and the last-bit write stores the least significant bit of the X2 register. Each register value can be programmed from 1 to 2,044 (IDT72V3656 4,092 (IDT72V3666 8,188 (IDT72V3676). TM ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 The state of the Port B data (B0-B17) outputs is controlled by the Port B Chip Select (CSB). The B0-B17 outputs are in the high-impedance state when CSB is HIGH. The B0-B17 outputs are active when CSB is LOW. ...

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... Almost-Empty flag and Almost-Full flag offset programming section). An Almost-Full flag is LOW when the number of words in its FIFO is greater than or equal to (2,048-Y), (4,096-Y), or (8,192-Y) for the IDT72V3656, IDT72V3666, or IDT72V3676 respectively. An Almost-Full flag is HIGH when the number of words in its FIFO is less than or equal to [2,048- 15 ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 (Y+1)], [4,096-(Y+1)], or [8,192-(Y+1)] for the IDT72V3656, IDT72V3666, or IDT72V3676 respectively. Note that a data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are required after a FIFO read for its Almost-Full flag to reflect the new level of fill ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 BYTE ORDER ON PORT A: BYTE ORDER ON PORT B: BE SIZEB SIZEB SIZEB SIZEB    A26 A18 A35 A27 A17 ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 BYTE ORDER ON PORT A: BYTE ORDER ON PORT C: BE SIZEC SIZEC SIZEC SIZEC   A26 A18  A35 A27 A17 ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLKA 1 CLKB t RSTS MRS1 BE/FWFT FS2,FS1 ,FS0 FFA/IRA EFB/ORB t RSF AEB t RSF AFA t RSF MBF1 RTM LOW LOOP HIGH NOTES: 1. PRS1 and MBC must be HIGH during Master Reset until the rising edge of FFA/IRA goes HIGH. ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLKA 1 CLKB t RSTS PRS1 FFA/IRA EFB/ORB t RSF AEB t RSF AFA t RSF MBF1 RTM LOW NOTES: 1. MRS1 must be HIGH during Partial Reset BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW. ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLKA 4 MRS1, MRS2 t FSS t FSH FS2 t FSS t FSH 0,0 FS1,FS0 FFA/IRA ENA A0-A35 CLKC FFC/IRC NOTES: is the minimum time between the rising CLKA edge and a rising CLKC edge for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising 1 ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLK t t CLKH CLKL CLKA FFA/IRA HIGH CSA W/RA MBA ENA A0-A35 NOTE: 1. Written to FIFO1. Figure 10. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes) ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLKC FFC/IRC HIGH t ENS2 MBC t ENS2 WENC t DS C0-C8 DATA SIZE TABLE FOR BYTE WRITES TO FIFO2 (1) SIZE MODE WRITE NO. SIZEC ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLKB EFB/ORB HIGH CSB MBB t ENS2 RENB t MDV t EN B0-B8 (Standard Mode) t MDV B0-B8 (FWFT Mode) NOTE: 1. Unused bytes B9-B17 are indeterminate for byte-size reads. ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLKA CSA LOW WRA HIGH t t ENS2 ENH MBA t t ENS2 ENH ENA IRA HIGH A0-A35 t SKEW1 CLKB FIFO1 Empty ORB ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLKA CSA LOW WRA HIGH t t ENH ENS2 MBA t t ENS2 ENH ENA FFA HIGH A0-A35 W1 t SKEW1 CLKB EFB FIFO1 Empty ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLKC t ENS2 MBC t ENS2 WENC IRC HIGH C0-C17 Write 1 Write 2 CLKA ORA FIFO2 Empty CSA LOW LOW W/RA LOW MBA ENA ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLKC t ENS2 MBC t ENS2 WENC FFC HIGH Write 1 C0-C17 Write 2 CLKA EFA FIFO2 Empty CSA LOW LOW W/RA LOW MBA ENA ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLK t t CLKH CLKL CLKB CSB LOW LOW MBB t ENS2 RENB ORB HIGH t A B0-B17 Previous Word in FIFO1 Output Register CLKA FIFO1 Full ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLK t t CLKH CLKL CLKB CSB LOW LOW MBB t ENS2 RENB EFB HIGH t A B0-B17 Previous Word in FIFO1 Output Register CLKA FFA FIFO1 Full ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLK t t CLKH CLKL CLKA CSA LOW W/RA LOW LOW MBA t ENS2 ENA ORA HIGH A0-A35 Previous Word in FIFO2 Output Register CLKC IRC FIFO2 Full ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA EFA HIGH A0-A35 Previous Word in FIFO2 Output Register t CLKC FFC FIFO2 Full ...

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... FIFO2 write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO Maximum FIFO Depth = 2,048 for the IDT72V3656, 4,096 for the IDT72V3666, 8,192 for the IDT72V3676. 4. Port C size is word or byte, AFC is set LOW by the last word or byte write of the long word, respectively. ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLKA t ENS1 CSA t ENS1 W/RA t ENS2 MBA t ENS2 ENA A0-A35 CLKB MBF1 CSB MBB RENB t EN FIFO1 Output Register B0-B17 NOTE Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data. If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs) ...

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... No more than D-2 may be written to the FIFO1 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, FFC will be LOW throughout the Retransmit setup procedure 2,048, 4,096 and 8,192 for the IDT72V3656, IDT72V3666 and IDT72V3676 respectively. Figure 31. Retransmit Timing for FIFO2 (IDT Standard Mode) ...

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... W1 = first word written to the FIFO2 after Master Reset on FIFO2 more than D-2 may be written to the FIFO2 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, IRC will be LOW throughout the Retransmit setup procedure 2,049, 4,097 and 8,193 for the IDT72V3656, IDT72V3666 and IDT72V3676 respectively. TM ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 CLK t t CLKH CLKL CLKA LOOP CSA W/RA MBA t ENS2 ENA t MDV t EN A0-A35 NOTES: 1. Data is read from FIFO2 and written into FIFO1 & placed on Port A simultaneously. The first data word written into FIFO1 is the Previous Data Word (Wn-1) 2 ...

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... IDT72V3656/72V3666/72V3676 3.3V CMOS TRIPLE BUS SyncFIFO WITH BUS MATCHING 2,048 4,096 and 8,192 PARAMETER MEASUREMENT INFORMATION From Output Timing 1.5V Input Data, 1.5V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1.5V t PZL t PLZ Low-Level ...

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ORDERING INFORMATION IDT XXXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range is available by special order. DATASHEET DOCUMENT HISTORY 06/14/2000 pgs. 1- 8-11, 13, 14, 16, 21, 22, 24-34, 37, and 39. 09/26/2000 pgs. ...