LTC2259-16 LINER [Linear Technology], LTC2259-16 Datasheet
LTC2259-16
Related parts for LTC2259-16
LTC2259-16 Summary of contents
Page 1
... V DD D15 • CORRECTION OUTPUT • LOGIC DRIVERS • D0 GND 225916 TA01a LTC2259-16 16-Bit, 80Msps Ultralow Power 1.8V ADC 2259- sampling 16-bit A/D converter de- allows undersampling of IF frequencies RMS – and ENC inputs may be driven differentially or 2-Tone FFT 70MHz and 75MHz – ...
Page 2
... LTC2259-16 ABSOLUTE MAXIMUM RATINGS Supply Voltages ( ....................... –0. – Analog Input Voltage ( PAR/SER, SENSE) (Note 3) .......... –0. CS, + – Digital Input Voltage (ENC , ENC SDI, SCK) (Note 4) .................................... –0.3V to 3.9V SDO (Note 4) ............................................. –0.3V to 3.9V PIN CONFIGURATION FULL-RATE CMOS OUTPUT MODE TOP VIEW ...
Page 3
... Figure 6 Test Circuit The l denotes the specifi cations which apply over the full operating temperature range, = –1dBFS. (Note 5) IN CONDITIONS 5MHz Input 70MHz Input 140MHz Input LTC2259-16 TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C MIN TYP MAX – ...
Page 4
... LTC2259-16 DYNAMIC ACCURACY otherwise specifi cations are 25° SYMBOL PARAMETER SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic Spurious Free Dynamic Range 4th Harmonic or Higher S/(N+D) Signal-to-Noise Plus Distortion Ratio INTERNAL REFERENCE CHARACTERISTICS full operating temperature range, otherwise specifi cations are at T ...
Page 5
... Sine Wave Input, OV =1. Input Sine Wave Input, OV =1.2V DD (Note 10) (Note 10) Sine Wave Input Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode LTC2259-16 MIN TYP MAX 200 l – 1.750 1.790 l 0.010 0.050 1 ...
Page 6
... LTC2259-16 TIMING CHARACTERISTICS range, otherwise specifi cations are at T SYMBOL PARAMETER f Sampling Frequency S t ENC Low Time (Note ENC High Time (Note Sample-and-Hold Acquisition Delay AP Time Digital Data Outputs (CMOS Modes: Full Data Rate and Double-Data Rate) t ENC to Data Delay ...
Page 7
... All Outputs Are Single-Ended and Have CMOS Levels N-5 N-5 N-4 N-4 N-3 D14 D15 D14 D15 D14 N-5 N-5 N-4 N-4 N LTC2259- – – 1 225916 TD01 N-3 N-2 N-2 D15 D14 D15 N-3 N-2 N-2 225916 TD02 225916f 7 ...
Page 8
... LTC2259-16 TIMING DIAGRAMS ANALOG INPUT – ENC + ENC + D0_1 – D0_1 • • • + D14_15 – D14_15 + CLKOUT – CLKOUT SCK SDI R SDO HIGH IMPEDANCE CS SCK SDI R/W SDO HIGH IMPEDANCE 8 Double-Data Rate LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels ...
Page 9
... IN 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 225916 G04 LTC2259-16: 8k Point 2-Tone FFT 70MHz, 75MHz, –1dBFS, IN 80Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 ...
Page 10
... Each Data Output 45 3.5mA LVDS 1.75mA LVDS 1.2V CMOS 5 1.8V CMOS SAMPLE RATE (Msps) LTC2259-16: SFDR vs Input Level 70MHz, 2V Range, 80Msps IN 110 100 dBFS dBc 300 350 –80 –70 –60 –50 –40 –30 –20 –10 ...
Page 11
... DD range. Connecting SENSE to ground selects the internal reference and a ±0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of ±0.8 • V LTC2259-16 ), SCK controls the DD ), SDO is not used DD should be used to bias the common CM ...
Page 12
... LTC2259-16 PIN FUNCTIONS FULL-RATE CMOS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND D15 (Pins 35, 36, 17-24, 29-34): Digital Outputs. D15 is the MSB the LSB. – CLKOUT (Pin 27): Inverted Version of CLKOUT + CLKOUT (Pin 28): Data Output Clock. The digital outputs ...
Page 13
... SENSE BUF APPLICATIONS INFORMATION CONVERTER OPERATION The LTC2259- low power 16-bit 80Msps A/D converter that is powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially, or single ended for lower power consumption. The digital outputs can be CMOS, ...
Page 14
... A/D input at its optimal CM 50Ω 0.1μ 0.1μF 25Ω 4.7pF 25Ω – 50Ω 0.1μF 0.1μF 2.7nH + A IN LTC2259-16 0.1μF 25Ω T1 0.1μF 25Ω 2.7nH – T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE LTC2259-16 225916 F04 225916 F06 225916f ...
Page 15
... A/D. Reference The LTC2259-16 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE For a 1V input range using the internal DD reference, connect SENSE to ground ...
Page 16
... V (up to 3.6V should have fast 0.1μF + ENC T1 1:4 100Ω 100Ω – ENC 0.1μF Figure 12. Sinusoidal Encode Drive 0.1μF + ENC PECL OR LTC2259-16 LVDS CLOCK 0.1μF – ENC 225916 F13 Figure 13. PECL or LVDS Encode Drive + threshold LTC2259-16 225916 F12 225916f ...
Page 17
... DIGITAL OUTPUTS Digital Output Modes The LTC2259-16 can operate in three digital output modes: full-rate CMOS, double-data rate CMOS (to halve the number of output lines), or double-data rate LVDS (to reduce digital noise in the system). The output mode is set by mode control register A3 (serial programming mode SCK (parallel programming mode) ...
Page 18
... CLKOUT signal may need to be phase shifted relative to the data output bits. Most FPGAs have this feature; this is generally the best place to adjust the timing. The LTC2259-16 can also phase shift the CLKOUT – OUT signals by serially programming mode control register A2. The output clock can be shifted by 0° ...
Page 19
... CLKOUT D15 D2 D14 225916 F15 LTC2259-16 PC BOARD CLKOUT FPGA D15 D2 D15 D14 D2 D14 • • • • • • LTC2259- 225916 F16 Figure 16. De-Randomizing a Randomized Digital Output Signal 225916f 19 ...
Page 20
... Nap mode is enabled by mode control register A1 in the serial programming mode. DEVICE PROGRAMMING MODES The operating modes of the LTC2259-16 can be pro- grammed by either a parallel interface or a simple serial interface. The serial interface has more fl exibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes ...
Page 21
... To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset is complete, bit D7 is automatically set back to zero Power-Down Control Bits LTC2259- PWROFF1 PWROFF0 225916f 21 ...
Page 22
... LTC2259-16 APPLICATIONS INFORMATION REGISTER A2: TIMING REGISTER (ADDRESS 02h Bits 7-4 Unused, Don’t Care Bits. Bit 3 CLKINV Output Clock Invert Bit 0 = Normal CLKOUT Polarity (as shown in the timing diagrams Inverted CLKOUT Polarity Bits 2-1 CLKPHASE1:CLKPHASE0 CLKOUT Delay (as shown in the timing diagrams) + – ...
Page 23
... HEAT TRANSFER Most of the heat generated by the LTC2259-16 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board ...
Page 24
... TYPICAL APPLICATIONS T2 MABAES0060 R9 10Ω • • R39 ANALOG INPUT 33.2Ω 1% R40 33.2Ω 1% R10 10Ω R15 100Ω C12 C13 0.1μF 1μF 24 LTC2259-16 Schematic SENSE C23 1μF R14 1k C51 4.7pF C17 1μF C19 0.1μ SENSE REF R27 10Ω ...
Page 25
... TYPICAL APPLICATIONS Silkscreen Top Inner Layer 2 GND 225916 TA03 225916 TA04 LTC2259-16 Top Side 225916 TA04 Inner Layer 3 225916 TA06 225916f 25 ...
Page 26
... LTC2259-16 TYPICAL APPLICATIONS Inner Layer 4 26 225916 TA07 Bottom Side 225916 TA09 Inner Layer 5 Power 225916 TA08 225916f ...
Page 27
... Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø) 0.70 ±0.05 6.50 ±0.05 5.10 ±0.05 4.50 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.75 ± 0. 0.10 TYP 4.50 REF (4-SIDES) 0.200 REF 0.00 – 0.05 LTC2259- 0.115 TYP 39 40 0.40 ± 0. PIN 1 NOTCH R = 0.45 OR 0.35 45° CHAMFER 4.42 ±0.10 4.42 ±0.10 (UJ40) QFN REV Ø 0406 0.25 ± 0.05 0.50 BSC BOTTOM VIEW— ...
Page 28
... C19 0.1μ SENSE REF CM R27 10Ω AIN R28 10Ω 2 – AIN 3 GND 4 REFH 5 C15 REFH C20 0.1μF LTC2259-16 2.2μF 6 REFL 7 REFL C21 PAR/SER 8 PAR/SER 0.1μ C18 0.1μF + – CS GND ENC ENC SCK ...