MPC8270 MOTOROLA [Motorola, Inc], MPC8270 Datasheet
MPC8270
Available stocks
Related parts for MPC8270
MPC8270 Summary of contents
Page 1
... This document contains detailed information about power considerations, DC/AC electrical characteristics, and AC timing specifications for .13µm (HiP7) members of the PowerQUICC II™ family of integrated communications processors—the MPC8280, the MPC8275, and the MPC8270 (collectively called 'the MPC8280' throughout this document ). The following topics are addressed: Topic Section 1, “ ...
Page 2
... packages—as shown in Table 2. Note that throughout this document references to the MPC8280 and the MPC8270 are inclusive of VR and ZQ package devices unless otherwise specified. For more information on VR and ZQ packages, contact your Motorola sales office. For package ordering information, refer to Section 10, “ ...
Page 3
... Notes: 1 MPC8280 only (not on MPC8270, the VR package, nor the ZQ package) 2 MPC8280 has 2 serial interface (SI) blocks and 8 TDM ports. MPC8270 and the VR and ZQ packages have only 1 SI block and 4 TDM ports (TDM2[A–D]). 3 MPC8280, MPC8275VR, MPC8275ZQ only (not on MPC8270, MPC8270VR, nor MPC8270ZQ) 1 ...
Page 4
High-performance (SPEC95 benchmark at 450 MHz; 855 Dhrystones MIPS at 450 MHz) — Supports bus snooping for data cache coherency — Floating-point unit (FPU) • Separate power supply for internal logic and for I/O • Separate PLLs for G2_LE ...
Page 5
... HDLC— rates (clear channel) – FCC2 can also be connected to the TC layer (MPC8280 only) — Two multichannel controllers (MCCs) (one MCC on the MPC8270) – Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split into four subgroups of 32 channels each. ...
Page 6
... One inter-integrated circuit (I – Microwire compatible – Multiple-master, single-master, and slave modes — eight TDM interfaces (four on the MPC8270) – Supports two groups of four TDM channels for a total of eight TDMs (one group of four on the MPC8270 and the MPC8275) – 2,048 bytes of SI RAM – ...
Page 7
Independent transmit and receive routing, frame synchronization – Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces — Eight ...
Page 8
Note that for extended temperature parts the range is (-40) NOTE: Core, PLL, and I/O Supply Voltages After power up sequence is complete, VDDH and VDD/VCCSYN must track each other and both voltages must vary in the same direction. ...
Page 9
Table 5. DC Electrical Characteristics Characteristic Hi-Z (off state) leakage current Signal low input current 0 Signal high input current 2 Output high voltage – except ...
Page 10
Table 5. DC Electrical Characteristics Characteristic I = 6.0mA ABB/IRQ2 TS A[0-31] TT[0-4] TBST TSIZE[0–3] AACK ARTRY DBG DBB/IRQ3 D[0-63] DP(0)/RSRV/EXT_BR2 DP(1)/IRQ1/EXT_BG2 DP(2)/TLBISYNC/IRQ2/EXT_DBG2 DP(3)/IRQ3/EXT_BR3/CKSTP_OUT DP(4)/IRQ4/EXT_BG3/CORE_SREST DP(5)/TBEN/EXT_DBG3/IRQ5/CINT DP(6)/CSE(0)/IRQ6 DP(7)/CSE(1)/IRQ7 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5/CINT CPU_DBG ...
Page 11
Table 5. DC Electrical Characteristics Characteristic I = 5.3mA OL CS[0-9] CS(10)/BCTL1 CS(11)/AP(0) BADDR[27–28] ALE BCTL0 PWE[0–7]/PSDDQM[0–7]/PBS[0–7] PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LWE[0–3]LSDDQM[0–3]/LBS[0–3]/PCI_CFG[0–3] LSDA10/LGPL0/PCI_MODCKH0 LSDWE/LGPL1/PCI_MODCKH1 LOE/LSDRAS/LGPL2/PCI_MODCKH2 LSDCAS/LGPL3/PCI_MODCKH3 LGTA/LUPMWAIT/LGPL4/LPBS LSDAMUX/LGPL5/PCI_MODCK LWR MODCK[1–3]/AP[1–3]/TC[0–2]/BNKSEL[0– 3.2mA OL L_A14/PAR L_A15/FRAME/SMI L_A16/TRDY L_A17/IRDY/CKSTP_OUT ...
Page 12
Thermal Characteristics Table 6 describes thermal characteristics for both the packages. See Table 2 for information about a given device’s package. For the discussions sections 4.1 and 4.2, P power dissipation of the I/O drivers. Characteristic Symbol Junction to ...
Page 13
Experimental Determination To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (Ψ measurement of the temperature at the top center of the package case using the following equation: T ...
Page 14
Power Dissipation Table 7 provides preliminary, estimated power dissipation for various configurations. Note that suitable thermal management is required to ensure the junction temperature does not exceed the maximum specified value. Also note that the I/O power should be ...
Page 15
CPM AC Characteristics Table 9 lists CPM output characteristics. Table 9. AC Characteristics for CPM Outputs Spec Number Characteristic Max Min sp36a sp37a FCC outputs—internal clock (NMSI) sp36b sp37b FCC outputs—external clock (NMSI) sp38a sp39a SCC/SMC/SPI/I2C outputs—internal clock (NMSI) ...
Page 16
Figure 3 shows the FCC internal clock. BRG_OUT sp16a FCC input signals FCC output signals Note: When GFMR[TCI FCC output signals Note: When GFMR.[TCI Figure 4 shows the FCC external clock. Serial ClKin sp16b FCC input ...
Page 17
Figure 5 shows the SCC/SMC/SPI/I Serial CLKin SCC/SMC/SPI/I2C input signals (See note) SCC/SMC/SPI/I2C output signals (See note) Note: There are four possible timing conditions for SCC and SPI: 1. Input sampled on the rising edge and output driven on the ...
Page 18
Figure 7 shows TDM input and output signals. Serial CLKin TDM input signals TDM output signals Note: There are four possible TDM timing conditions: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. ...
Page 19
SIU AC Characteristics The CLKIN input to the MPC8280 should not exceed +/– 150 psec. This represents total input jitter—the combination of short term (peak-to-peak) and long term (cumulative). The duty cycle of CLKIN should not exceed the ratio ...
Page 20
Table 12 lists SIU output characteristics. Table 12. AC Characteristics for SIU Outputs Spec Number Characteristic Max Min sp31 sp30 PSDVAL/TEA/TA sp32 sp30 ADD/ADD_atr./BADDR/CI/GBL/WT sp33a sp30 Data bus sp33b sp30 DP sp34 sp30 Memory controller signals/ALE sp35 sp30 All other ...
Page 21
Figure 9 shows the interaction of several bus signals. CLKin AACK/TA/TS/ DBG/BG/BR input signals ARTRY/TEA input signals DATA bus normal mode input signal All other input signals PSDVAL/TEA/TA output signals ADD/ADD_atr/BADDR/CI/ GBL/WT output signals DATA bus output signals All other ...
Page 22
Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity). CLKin DATA bus, ECC, and PARITY mode input signals Pipeline mode— DATA bus, ECC, and PARITY mode input signals DP mode input signal Pipeline ...
Page 23
Table 13. Tick Spacing for Memory Controller Signals PLL Clock Ratio 1:2, 1:3, 1:4, 1:5, 1:6 1:2.5 1:3.5 Figure representation of the information in Table 13. CLKin T1 CLKin T1 CLKin T1 Figure 12. Internal Tick Spacing ...
Page 24
In each clocking mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits during the power-up reset—three hardware configuration pins (MODCK[1–3]) and four bits from hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers ...
Page 25
Table 15. Clock Configurations for Local Bus Mode Bus Clock 2 Mode (MHz) MODCK_H-MODCK[1-3] low 0010_010 62.5 0010_011 50.0 0010_100 41.7 0010_101 35.7 0010_110 33.3 0010_111 0011_000 50.0 0011_001 41.7 0011_010 35.7 0011_011 31.3 0011_100 0011_101 0011_110 41.7 0011_111 35.7 ...
Page 26
Table 15. Clock Configurations for Local Bus Mode Bus Clock 2 Mode (MHz) MODCK_H-MODCK[1-3] low 0111_011 55.5 0111_100 71.4 0111_101 62.5 0111_110 55.6 0111_111 1000_000 1000_001 1000_010 71.4 1000_011 62.5 1000_100 55.6 1000_101 50.0 1000_110 45.5 1100_000 1100_001 1100_010 1101_000 ...
Page 27
In PCI mode only, PCI_MODCK comes from the LGPL5 pin and MODCK_H[0–3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}. The minimum Tval = 2 when PCI_MODCK = 1, and the minimum Tval = 1 when PCI_MODCK = 0. Therefore, designers should ...
Page 28
Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 4 Bus Clock 3 Mode CPM (MHz) Multiplication MODCK_H- Factor low high MODCK[1-3] 0011_001 50.0 66.7 0011_010 50.0 66.7 0011_011 50.0 66.7 0100_000 0100_001 50.0 66.7 0100_010 50.0 66.7 0100_011 50.0 ...
Page 29
Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 4 Bus Clock 3 Mode CPM (MHz) Multiplication MODCK_H- Factor low high MODCK[1-3] 1000_100 66.7 88.9 1000_101 66.7 88.9 1000_110 66.7 88.9 1001_000 66.7 76.2 1001_001 57.1 76.2 1001_010 71.4 76.2 ...
Page 30
Table 16. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 4 Bus Clock 3 Mode (MHz) Multiplication MODCK_H- Factor low high MODCK[1-3] 1101_101 125.0 166.7 1101_110 125.0 166.7 1110_000 100.0 133.3 1110_001 100.0 133.3 1110_010 100.0 133.3 1110_011 100.0 133.3 1110_100 ...
Page 31
Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 4 Bus Clock 3 Mode (MHz) Multiplication MODCK_H- Factor low high MODCK[1-3] 0000_101 55.5 100.0 0000_110 71.4 100.0 0000_111 62.5 100.0 0001_000 50.0 100.0 0001_001 50.0 100.0 0001_010 50.0 100.0 0001_011 ...
Page 32
Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 4 Bus Clock 3 Mode (MHz) Multiplication MODCK_H- Factor low high MODCK[1-3] 0110_000 66.7 120.0 0110_001 60.0 120.0 0110_010 71.4 120.0 0110_011 62.5 120.0 0110_100 60.0 120.0 0110_101 60.0 120.0 0110_110 ...
Page 33
Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=1) 4 Bus Clock 3 Mode (MHz) Multiplication MODCK_H- Factor low high MODCK[1-3] 1010_000 75.0 150.0 1010_001 75.0 150.0 1010_010 75.0 150.0 1010_011 75.0 150.0 1010_100 75.0 150.0 1011_000 1011_001 80.0 160.0 ...
Page 34
The minimum bus frequency guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock mode. For modes with a CPU multiplication factor ...
Page 35
Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) PCI Clock 3 Mode CPM (MHz) Multiplication MODCK_H- Factor low high MODCK[1-3] 0001_010 0001_011 0001_100 66.7 66.7 0010_001 50.0 66.7 0010_010 59.5 66.7 0010_011 52.1 66.7 0010_100 50.0 66.7 0011_000 0011_001 ...
Page 36
Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) PCI Clock 3 Mode CPM (MHz) Multiplication MODCK_H- Factor low high MODCK[1-3] 0110_100 50.0 66.7 0111_000 55.5 66.7 0111_001 50.0 66.7 0111_010 50.0 66.7 0111_011 50.0 66.7 1000_000 1000_001 66.7 66.7 ...
Page 37
Table 18. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) PCI Clock 3 Mode CPM (MHz) Multiplication MODCK_H- Factor low high MODCK[1-3] 1100_110 50.0 66.7 1100_111 50.0 66.7 1101_000 50.0 66.7 1101_001 50.0 66.7 1101_010 50.0 66.7 1101_011 50.0 66.7 1101_100 ...
Page 38
Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) PCI Clock 3 Mode CPM (MHz) Multiplication MODCK_H- Factor low high MODCK[1-3] 0000_000 33.3 50.0 0000_001 33.3 50.0 0000_010 27.8 50.0 0000_011 31.3 50.0 0000_100 25.0 50.0 0000_101 29.8 50.0 0000_110 ...
Page 39
Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) PCI Clock 3 Mode CPM (MHz) Multiplication MODCK_H- Factor low high MODCK[1-3] 0101_001 27.8 50.0 0101_010 35.7 50.0 0101_011 31.3 50.0 0101_100 27.8 50.0 0101_101 27.8 50.0 0101_110 27.8 50.0 0110_000 ...
Page 40
Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) PCI Clock 3 Mode CPM (MHz) Multiplication MODCK_H- Factor low high MODCK[1-3] 1010_010 26.8 50.0 1010_011 25.0 50.0 1010_100 25.0 50.0 1011_000 1011_001 25.0 50.0 1011_010 25.0 50.0 1011_011 25.0 50.0 ...
Page 41
... ZU Package—MPC8280 and MPC8270 The following figures and table represent the standard 480 TBGA package. For information on the alternate package, refer to Section 8.2, “VR and ZQ Packages—MPC8275 and MPC8270” on page 56. Figure 13 shows the pinout of the ZU package as viewed from the top surface. ...
Page 42
...
Page 43
... Table 20 shows the pinout list of the MPC8280 and MPC8270. Table 21 defines conventions and acronyms used in Table 20. Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List MPC8280/MPC8270 BR BG ABB/IRQ2 A10 A11 A12 A13 A14 A15 A16 A17 A18 ...
Page 44
... Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued) MPC8280/MPC8270 A28 A29 A30 A31 TT0 TT1 TT2 TT3 TT4 TBST TSIZ0 TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBG DBB/IRQ3 D10 D11 D12 D13 D14 D15 44 MPC8280 PowerQUICC II™ Family Hardware Specifications ...
Page 45
... Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued) MPC8280/MPC8270 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 ...
Page 46
... Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued) MPC8280/MPC8270 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DP0/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET/EXT_BG3 IRQ5/CINT/DP5/TBEN/EXT_DBG3 IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5/CINT CPU_DBG CPU_BR CS0 ...
Page 47
... Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued) MPC8280/MPC8270 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10/BCTL1 CS11/AP0 BADDR27 BADDR28 ALE BCTL0 PWE0/PSDDQM0/PBS0 PWE1/PSDDQM1/PBS1 PWE2/PSDDQM2/PBS2 PWE3/PSDDQM3/PBS3 PWE4/PSDDQM4/PBS4 PWE5/PSDDQM5/PBS5 PWE6/PSDDQM6/PBS6 PWE7/PSDDQM7/PBS7 PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LWE0/LSDDQM0/LBS0/PCI_CFG0 LWE1/LSDDQM1/LBS1/PCI_CFG1 LWE2/LSDDQM2/LBS2/PCI_CFG2 LWE3/LSDDQM3/LBS3/PCI_CFG3 ...
Page 48
... Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued) MPC8280/MPC8270 LOE/LSDRAS/LGPL2/PCI_MODCKH2 LSDCAS/LGPL3/PCI_MODCKH3 LGTA/LUPMWAIT/LGPL4/LPBS LGPL5/LSDAMUX/PCI_MODCK LWR L_A14/PAR L_A15/FRAME/SMI L_A16/TRDY L_A17/IRDY/CKSTP_OUT L_A18/STOP L_A19/DEVSEL L_A20/IDSEL L_A21/PERR L_A22/SERR L_A23/REQ0 L_A24/REQ1/HSEJSW L_A25/GNT0 L_A26/GNT1/HSLED L_A27/GNT2/HSENUM L_A28/RST/CORE_SRESET L_A29/INTA L_A30/REQ2 L_A31/DLLOUT LCL_D0/AD0 LCL_D1/AD1 LCL_D2/AD2 LCL_D3/AD3 LCL_D4/AD4 LCL_D5/AD5 LCL_D6/AD6 LCL_D7/AD7 LCL_D8/AD8 ...
Page 49
... Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued) MPC8280/MPC8270 LCL_D11/AD11 LCL_D12/AD12 LCL_D13/AD13 LCL_D14/AD14 LCL_D15/AD15 LCL_D16/AD16 LCL_D17/AD17 LCL_D18/AD18 LCL_D19/AD19 LCL_D20/AD20 LCL_D21/AD21 LCL_D22/AD22 LCL_D23/AD23 LCL_D24/AD24 LCL_D25/AD25 LCL_D26/AD26 LCL_D27/AD27 LCL_D28/AD28 LCL_D29/AD29 LCL_D30/AD30 LCL_D31/AD31 LCL_DP0/C0/BE0 LCL_DP1/C1/BE1 LCL_DP2/C2/BE2 LCL_DP3/C3/BE3 IRQ0/NMI_OUT IRQ7/INT_OUT/APE 1 TRST ...
Page 50
... Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued) MPC8280/MPC8270 HRESET SRESET QREQ RSTCONF MODCK1/AP1/TC0/BNKSEL0 MODCK2/AP2/TC1/BNKSEL1 MODCK3/AP3/TC2/BNKSEL2 CLKIN1 PA0/RESTART1/DREQ3 PA1/REJECT1/DONE3 PA2/CLK20/DACK3 PA3/CLK19/DACK4/L1RXD1A2 PA4/REJECT2/DONE4 PA5/RESTART2/DREQ4 PA6/FCC2_RXADDR3 PA7/SMSYN2/FCC2_TXADDR3 PA8/SMRXD2/FCC2_TXADDR4 PA9/SMTXD2 PA10/MSNUM5 PA11/MSNUM4 PA12/MSNUM3 PA13/MSNUM2 PA14/FCC1_MII_HDLC_RXD3 PA15/FCC1_MII_HDLC_RXD2 PA16/FCC1_MII_HDLC_RXD1/ FCCI_RMII_RXD1 PA17/FCC1_MII_HDLC_RXD0/ FCC1_MII_TRAN_RXD/ FCCI_RMII_RXD0 PA18/FCC1_MII_HDLC_TXD0/ FCC1_MII_TRAN_TXD/ FCC1_RMII_TXD0 50 MPC8280 PowerQUICC II™ ...
Page 51
... Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued) MPC8280/MPC8270 PA19/FCC1_MII_HDLC_TXD1/ FCC1_RMII_TXD1 PA20/FCC1_MII_HDLC_TXD2 PA21/FCC1_MII_HDLC_TXD3 PA22 PA23 PA24/MSNUM1 PA25/MSNUM0 PA26/FCC1_RMII_RX_ER PA27/FCC1_MII_RX_DV/ FCC1_RMII_CRS_DV PA28/FCC1_MII_TX_EN/ FCC1_RMII_TX_EN PA29/FCC1_MII_TX_ER PA30/FCC1_MII_CRS/FCC1_RTS PA31/FCC1_MII_COL PB4/FCC3_MII_HDLC_TXD3/ L1RSYNCA2/FCC3_RTS PB5/FCC3_MII_HDLC_TXD2/ L1TSYNCA2/L1GNTA2 PB6/FCC3_MII_HDLC_TXD1/ FCC3_RMII_TXD1/ L1RXDA2/L1RXD0A2 PB7/FCC3_MII_HDLC_TXD0/ FCC3_RMII_TXD0/ FCC3_TXD/L1TXDA2/L1TXD0A2 PB8/FCC3_MII_HDLC_RXD0/ FCC3_RMII_RXD0/ FCC3_RXD/TXD3 PB9/FCC3_MII_HDLC_RXD1/ FCC3_RMII_RXD1/L1TXD2A2 PB10/FCC3_MII_HDLC_RXD2 ...
Page 52
... Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued) MPC8280/MPC8270 PB16/FCC3_MII_RMII_RX_ER/CLK18 PB17/FCC3_MII_RX_DV/CLK17/ FCC3_RMII_CRS_DV PB18/FCC2_MII_HDLC_RXD3/ L1CLKOD2/L1RXD2A2 PB19FCC2_MII_HDLC_RXD2/ L1RQD2/L1RXD3A2 PB20/FCC2_MII_HDLC_RMII_RXD1/ L1RSYNCD2 PB21//FCC2_MII_HDLC_RMII_RXD0/ FCC2_TRAN_RXD/L1TSYNCD2/ L1GNTD2 PB22/FCC2_MII_HDLC_TXD0/ FCC2_TXD/FCC2_RMII_TXD0/ L1RXDD2 PB23/FCC2_MII_HDLC_TXD1/ L1RXD2A1/L1TXDD2/ FCC2_RMII_TXD1 PB24/FCC2_MII_HDLC_TXD2/ L1RSYNCC2 PB25/FCC2_MII_HDLC_TXD3/ L1TSYNCC2/L1GNTC2 PB26/FCC2_MII_CRS/L1RXDC2 PB27/FCC2_MII_COL/L1TXDC2 PB28/FCC2_MII_RX_ER/ FCC2_RMII_RX_ER/FCC2_RTS/ L1TSYNCB2/L1GNTB2/TXD1 PB29/L1RSYNCB2/FCC2_MII_TX_EN/ FCC2_RMII_TX_EN PB30/FCC2_MII_RX_DV/ FCC2_RMII_CRS_DV/L1RXDB2 ...
Page 53
... Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued) MPC8280/MPC8270 PC5/SI2_L1ST3/FCC2_CTS PC6/FCC1_CD PC7/FCC1_CTS PC8/CD4/RENA4/SI2_L1ST2/CTS3/ USBRN PC9/CTS4/CLSN4/SI2_L1ST1/ L1TSYNCA2/L1GNTA2/USB_RP PC10/CD3/RENA3 PC11/CTS3/CLSN3/L1TXD3A2 PC12/CD2/RENA2 PC13/CTS2/CLSN2 PC14/CD1/RENA1 PC15/CTS1/CLSN1/SMTXD2 PC16/CLK16/TIN4 PC17/CLK15/TIN3/BRGO8 PC18/CLK14/TGATE2 PC19/CLK13/BRGO7/SPICLK PC20/CLK12/TGATE1/USB_OE PC21/CLK11/BRGO6 PC22/CLK10/DONE1/FCC1_UT_TXPRTY PC23/CLK9/BRGO5/DACK1 PC24/CLK8/TOUT4 PC25/CLK7/BRGO4 PC26/CLK6/TOUT3/TMCLK PC27/FCC3_TXD/FCC3_MII_TXD0/ FCC3_RMII_TXD0/CLK5/BRGO3 PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2/ FCC2_RXADDR4 PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 MOTOROLA MPC8280 PowerQUICC II™ Family Hardware Specifications ...
Page 54
... Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued) MPC8280/MPC8270 PC30/CLK2/TOUT1 PC31/CLK1/BRGO1 PD4/BRGO8/FCC3_RTS/SMRXD2 PD5/DONE1 PD6/DACK1 PD7/SMSYN1/FCC1_TXCLAV2 PD8/SMRXD1/BRGO5 PD9/SMTXD1/BRGO3 PD10/L1CLKOB2/BRGO4 PD11/L1RQB2 PD12 PD13 PD14/L1CLKOC2/I2CSCL PD15/L1RQC2/I2CSDA PD16/SPIMISO PD17/BRGO2/SPIMOSI PD18/SPICLK PD19/SPISEL/BRGO1 PD20/RTS4/TENA4/L1RSYNCA2/ USB_TP PD21/TXD4/L1RXD0A2/L1RXDA2/ USB_TN PD22/RXD4L1TXD0A2/L1TXDA2/ USB_RXD PD23/RTS3/TENA3 PD24/TXD3 PD25/RXD3 54 MPC8280 PowerQUICC II™ Family Hardware Specifications ...
Page 55
... Table 20. MPC8280 and MPC8270 (ZU Package) Pinout List (Continued) MPC8280/MPC8270 PD26/RTS2/TENA2 PD27/TXD2 PD28/RXD2 PD29/RTS1/TENA1 PD30/TXD1 PD31/RXD1 VCCSYN VCCSYN1 CLKIN2 3 SPARE4 4 PCI_MODE 3 SPARE6 5 No connect I/O power Core power Ground 1 Should be tied to VDDH via a 2K Ω external pull-up resistor. 2 The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive DC current recommended to either pull unused pins to GND or VDDH confi ...
Page 56
... VR and ZQ Packages—MPC8275 and MPC8270 The following figures and table represent the alternate 516 PBGA package. For information on the standard package for the MPC8280 and the MPC8270, refer to Section 8.1, “ZU Package—MPC8280 and MPC8270” on page 41. Figure 15 shows the pinout of the VR and ZQ packages as viewed from the top surface. ...
Page 57
...
Page 58
... PowerQUICC II packages. Users should consult “Motorola PowerQUICC II™ Pb-Free Packaging Information” (MPC8250PBFREEPKG) available at www.motorola.com/semiconductors. Table 22 shows the pinout list of the MPC8275 and MPC8270. Table 21 defines conventions and acronyms used in Table 22. Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List MPC8275/MPC8270 ...
Page 59
... Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued) MPC8275/MPC8270 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 TT0 TT1 TT2 TT3 TT4 TBST TSIZ0 TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBG DBB/IRQ3 MOTOROLA MPC8280 PowerQUICC II™ Family Hardware Specifications ...
Page 60
... Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued) MPC8275/MPC8270 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 ...
Page 61
... Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued) MPC8275/MPC8270 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DP0/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET/EXT_BG3 IRQ5/CINT/DP5/TBEN/EXT_DBG3 IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 PSDVAL TA TEA GBL/IRQ1 ...
Page 62
... Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued) MPC8275/MPC8270 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5/CINT CPU_DBG CPU_BR CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10/BCTL1 CS11/AP0 BADDR27 BADDR28 ALE BCTL0 PWE0/PSDDQM0/PBS0 PWE1/PSDDQM1/PBS1 PWE2/PSDDQM2/PBS2 PWE3/PSDDQM3/PBS3 PWE4/PSDDQM4/PBS4 PWE5/PSDDQM5/PBS5 PWE6/PSDDQM6/PBS6 PWE7/PSDDQM7/PBS7 PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 ...
Page 63
... Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued) MPC8275/MPC8270 LWE0/LSDDQM0/LBS0/PCI_CFG0 LWE1/LSDDQM1/LBS1/PCI_CFG1 LWE2/LSDDQM2/LBS2/PCI_CFG2 LWE3/LSDDQM3/LBS3/PCI_CFG3 LSDA10/LGPL0/PCI_MODCKH0 LSDWE/LGPL1/PCI_MODCKH1 LOE/LSDRAS/LGPL2/PCI_MODCKH2 LSDCAS/LGPL3/PCI_MODCKH3 LGTA/LUPMWAIT/LGPL4/LPBS LGPL5/LSDAMUX/PCI_MODCK LWR L_A14/PAR L_A15/FRAME/SMI L_A16/TRDY L_A17/IRDY/CKSTP_OUT L_A18/STOP L_A19/DEVSEL L_A20/IDSEL L_A21/PERR L_A22/SERR L_A23/REQ0 L_A24/REQ1/HSEJSW L_A25/GNT0 L_A26/GNT1/HSLED L_A27/GNT2/HSENUM L_A28/RST/CORE_SRESET L_A29/INTA L_A30/REQ2 L_A31/DLLOUT LCL_D0/AD0 LCL_D1/AD1 ...
Page 64
... Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued) MPC8275/MPC8270 LCL_D5/AD5 LCL_D6/AD6 LCL_D7/AD7 LCL_D8/AD8 LCL_D9/AD9 LCL_D10/AD10 LCL_D11/AD11 LCL_D12/AD12 LCL_D13/AD13 LCL_D14/AD14 LCL_D15/AD15 LCL_D16/AD16 LCL_D17/AD17 LCL_D18/AD18 LCL_D19/AD19 LCL_D20/AD20 LCL_D21/AD21 LCL_D22/AD22 LCL_D23/AD23 LCL_D24/AD24 LCL_D25/AD25 LCL_D26/AD26 LCL_D27/AD27 LCL_D28/AD28 LCL_D29/AD29 LCL_D30/AD30 LCL_D31/AD31 LCL_DP0/C0/BE0 LCL_DP1/C1/BE1 ...
Page 65
... Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued) MPC8275/MPC8270 TCK TMS TDI TDO TRIS 1 PORESET HRESET SRESET QREQ RSTCONF MODCK1/AP1/TC0/BNKSEL0 MODCK2/AP2/TC1/BNKSEL1 MODCK3/AP3/TC2/BNKSEL2 CLKIN1 PA0/RESTART1/DREQ3 PA1/REJECT1/DONE3 PA2/CLK20/DACK3 PA3/CLK19/DACK4/L1RXD1A2 PA4/REJECT2/DONE4 PA5/RESTART2/DREQ4 PA6 PA7/SMSYN2 PA8/SMRXD2 PA9/SMTXD2 PA10/MSNUM5 PA11/MSNUM4 PA12/MSNUM3 PA13/MSNUM2 PA14/FCC1_MII_HDLC_RXD3 PA15/FCC1_MII_HDLC_RXD2 PA16/FCC1_MII_HDLC_RXD1/ ...
Page 66
... Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued) MPC8275/MPC8270 PA17/FCC_MII_HDLC_RXD0/ FCC1_MII_TRAN_RXD/ FCCI_RMII_RXD0 PA18/FCC1_MII_HDLC_TXD0/ FCC1_MIITRAN_TXD/ FCC1_RMII_TXD0 PA19/FCC1_MII_HDLC_TXD1/ FCC1_RMII_TXD1 PA20/FCC1_MII_HDLC_TXD2 PA21/FCC1_MII_HDLC_TXD3 PA22 PA23 PA24/MSNUM1 PA25/MSNUM0 PA26/FCC1_MII_RMII_RX_ER/ PA27/FCC1_MII_RX_DV/ FCC1_RMII_CRS_DV PA28/FCC1_MII_TX_EN/ FCC1_RMII_TX_EN PA29/FCC1_MII_TX_ER PA30/FCC1_MII_CRS/FCC1_RTS PA31/FCC1_MII_COL PB4/FCC3_MII_HDLC_TXD3/ L1RSYNCA2/FCC3_RTS PB5/FCC3_MII_HDLC_TXD2/ L1TSYNCA2/L1GNTA2 PB6/FCC3_MII_HDLC_TXD1/ FCC3_RMII_TXD1/ L1RXDA2/L1RXD0A2 PB7/FCC3_MII_HDLC_TXD0/ FCC3_RMII_TXD0/ ...
Page 67
... Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued) MPC8275/MPC8270 PB11/FCC3_MII_HDLC_RXD3 PB12/FCC3_MII_CRS/TXD2 PB13/FCC3_MII_COL/L1TXD1A2 PB14/FCC3_MII_RMII_TX_EN/RXD3 PB15/FCC3_MII_TX_ER/RXD2 PB16/FCC3_MII_RMII_RX_ER/CLK18 PB17/FCC3_MII_RX_DV/CLK17/ FCC3_RMII_CRS_DV PB18/FCC2_MII_HDLC_RXD3/ L1CLKOD2/L1RXD2A2 PB19FCC2_MII_HDLC_RXD2/ L1RQD2/L1RXD3A2 PB20/FCC2_MII_HDLC_RMII_RXD1/ L1RSYNCD2 PB21//FCC2_MII_HDLC_RMII_RXD0/ FCC2_TRAN_RXD/L1TSYNCD2/ L1GNTD2 PB22/FCC2_MII_HDLC_RMII_TXD0/ FCC2_TXD/FCC2_RMII_TXD0/ L1RXDD2 PB23/FCC2_MII_HDLC_TXD1/ L1RXD2A1/L1TXDD2/ FCC2_RMII_TXD1 PB24/FCC2_MII_HDLC_TXD2/ L1RSYNCC2 PB25/FCC2_MII_HDLC_TXD3/ L1TSYNCC2/L1GNTC2 PB26/FCC2_MII_CRS/L1RXDC2 PB27/FCC2_MII_COL/L1TXDC2 PB28/FCC2_MII_RX_ER/FCC2_RMII_RX_ER/ ...
Page 68
... Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued) MPC8275/MPC8270 PC3/FCC3_CTS/DACK2/CTS4/ USB_RP PC4/SI2_L1ST4/FCC2_CD PC5/SI2_L1ST3/FCC2_CTS PC6/FCC1_CD PC7/FCC1_CTS PC8/CD4/RENA4/SI2_L1ST2/CTS3/ USB_RN PC9/CTS4/CLSN4/SI2_L1ST1/ L1TSYNCA2/L1GNTA2/USB_RP PC10/CD3/RENA3 PC11/CTS3/CLSN3/L1TXD3A2 PC12/CD2/RENA2 PC13/CTS2/CLSN2 PC14/CD1/RENA1 PC15/CTS1/CLSN1/SMTXD2 PC16/CLK16/TIN4 PC17/CLK15/TIN3/BRGO8 PC18/CLK14/TGATE2 PC19/CLK13/BRGO7/SPICLK PC20/CLK12/TGATE1/USB_OE PC21/CLK11/BRGO6 PC22/CLK10/DONE1 PC23/CLK9/BRGO5/DACK1 PC24/CLK8/TOUT4 PC25/CLK7/BRGO4 PC26/CLK6/TOUT3/TMCLK PC27/FCC3_TXD/FCC3_MII_TXD0/ FCC3_RMII_TXD0/CLK5/BRGO3 68 MPC8280 PowerQUICC II™ Family Hardware Specifications ...
Page 69
... Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued) MPC8275/MPC8270 PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2 FCC2_UT_RXADDR4 PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 PC30/CLK2/TOUT1 PC31/CLK1/BRGO1 PD4/BRGO8/FCC3_RTS/SMRXD2 PD5/DONE1 PD6/DACK1 PD7/SMSYN1/FCC1_TXCLAV2 PD8/SMRXD1/BRGO5 PD9/SMTXD1/BRGO3 PD10/L1CLKOB2/BRGO4 PD11/L1RQB2 PD12 PD13 PD14/L1CLKOC2/I2CSCL PD15/L1RQC2/I2CSDA PD16/SPIMISO PD17/BRGO2/SPIMOSI PD18/SPICLK PD19/SPISEL/BRGO1 PD20/RTS4/TENA4/L1RSYNCA2/ USB_TP PD21/TXD4/L1RXD0A2/L1RXDA2/ USB_TN PD22/RXD4L1TXD0A2/L1TXDA2/ USB_RXD PD23/RTS3/TENA3 PD24/TXD3 MOTOROLA MPC8280 PowerQUICC II™ Family Hardware Specifications ...
Page 70
... Table 22. MPC8275 and MPC8270 (VR and ZQ Packages) Pinout List (Continued) MPC8275/MPC8270 PD25/RXD3 PD26/RTS2/TENA2 PD27/TXD2 PD28/RXD2 PD29/RTS1/TENA1 PD30/TXD1 PD31/RXD1 VCCSYN VCCSYN1 CLKIN2 3 SPARE4 4 PCI_MODE 3 SPARE6 5 No connect I/O power Core Power Ground 70 MPC8280 PowerQUICC II™ Family Hardware Specifications Pin Name MPC8275 only FCC1_UT16_TXD6 ...
Page 71
... GND with the noise filtering capacitors. 7 XFC (A18) pin: This pin is used in MPC826x(A) devices not used in MPC8275/MPC8270 because there is no need for external capacitor to operate the PLL. New designs should connect A18 (XFC) pin to GND. Old designs in which the MPC8275/MPC8270 is used as a drop-in replacement can leave the pin connected to the current capacitor ...
Page 72
Mechanical Dimensions Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA (ZU) package. Refer to Table 2. Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature—480 TBGA Figure 18 provides the mechanical dimensions and bottom ...
Page 73
Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature—516 PBGA MOTOROLA MPC8280 PowerQUICC II™ Family Hardware Specifications Package Description 73 ...
Page 74
... Table 22, “VR Pinout”: Addition of C18 to the Ground (GND) pin list (page 63) 0.3 6/2003 • Removal of notes stating “no local bus” on VR-package devices. The MPC8270VR and the MPC8275VR have local bus support. • References to “G2 core” changed to “G2_LE core.” Refer to the G2 Core Reference Manual (G2CORERM/D). • ...
Page 75
Revision Date 1.0 2/2004 • Removal of “Advance Information” and “Preliminary.” The MPC8280 is fully qualified. • Table 1: New • Figure 1: Modification to note 2 • Section 1.1: Core frequency range is 166–450 MHz • Addition of ZQ ...
Page 76
HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-480-768-2130 (800) 521-6274 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon ...