mpc8378 Freescale Semiconductor, Inc, mpc8378 Datasheet
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mpc8378 Summary of contents
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... Mbps Ethernet interfaces, a DDR1/DDR2 SDRAM memory controller, a flexible, a 32-bit local bus controller, a 32-bit PCI controller, an optional dedicated security engine, a USB © Freescale Semiconductor, Inc., 2008–2010. All rights reserved. Document Number: MPC8377EEC Rev. 3, 03/2010 Contents 1 ...
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Overview 2.0 dual-role controller, a programmable interrupt controller, dual I controller, an enhanced secured digital host controller, and a general-purpose I/O port. The block diagram of the MPC8377E is shown in Figure DUART 2 Dual I Timers GPIO SPI Interrupt ...
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... In addition to the security engine, new high-speed interfaces such as PCI Express and SATA are included. Table 1 compares the differences between MPC837xE derivatives and provides the number of ports available for each interface. Table 1. High-Speed Interfaces on the MPC8377E, MPC8378E, and MPC8379E Descriptions SGMII PCI Express® ...
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Overview 1.3 Dual Enhanced Three-Speed Ethernet Controllers (eTSECs) The eTSECs include the following features: • Two enhanced Ethernet interfaces can be used for RGMII/MII/RMII/RTBI • Two controllers conform to IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z, IEEE 802.3au, ...
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There are two I C controllers. These synchronous, multi-master buses can be connected to additional devices for expansion and system development. The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550 programming models. 16-byte FIFOs are ...
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Overview 1.10 PCI Express Controller The PCI Express controller includes the following features: • PCI Express 1.0a compatible Two ×1 links or one ×2 link width • • Auto-detection of number of connected lanes • Selectable operation as root complex ...
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Enhanced Secured Digital Host Controller (eSDHC) The enhanced SD Host Controller (eSDHC) has the following features: • Conforms to SD Host Controller Standard Specification, Rev 2.0 with Test Event register support. • Compatible with the MMC System Specification, Rev ...
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Electrical Characteristics Table 2. Absolute Maximum Ratings Characteristic Input voltage DDR DRAM signals DDR DRAM reference Three-speed Ethernet signals PCI, DUART, CLKIN, system control and power 2 management and JTAG signals Local Bus Storage temperature range Notes: 1 ...
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Table 3. Recommended Operating Conditions (continued) Characteristic Local Bus SerDes Operating temperature range Notes and V must track each other and must vary in the same direction—either in the positive or negative DD ...
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Electrical Characteristics 2.1.3 Output Driver Characteristics Table 4 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Driver Type Local bus interface utilities signals PCI signals DDR1 signal DDR2 signal eTSEC 10/100/1000 signals 2 ...
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Please note that the SerDes power supply (L[1,2]_nV ( The opposite sequence applies to the power down requirements. The I/O supplies must go down first and immediately followed by the core and PLL supplies. 3 Power Characteristics The ...
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Power Characteristics Table 6 shows the estimated typical I/O power dissipation for the device. Table 6. MPC8377E Typical I/O Power Dissipation GV DD Interface Parameter (1.8 V) 200 MHz data 0.28 rate, 32-bit 200 MHz data 0.41 rate, 64-bit 266 ...
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Table 6. MPC8377E Typical I/O Power Dissipation (continued Interface Parameter (1.8 V) MII or RMII — eTSEC I/O Load = 25 pf RGMII or — RTBI USB 12 Mbps — (60MHz 480 Mbps — Clock) SerDes per lane ...
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Clock Input Timing 4.2 AC Electrical Characteristics The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. (CLKIN/PCI_CLK) AC timing ...
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RESET Initialization This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the MPC8377E. 5.1 RESET DC Electrical Characteristics Table 10 provides the DC electrical characteristics for the RESET pins of ...
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DDR1 and DDR2 SDRAM Table 11. RESET Initialization Timing Specifications (continued) Parameter/Condition Time for the device to turn off POR config signals with respect to the assertion of HRESET Time for the device to start driving functional output signals multiplexed ...
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Table 13. DDR2 SDRAM DC Electrical Characteristics for GV Parameter Output low current (V = 0.3 V) OUT Note expected to be within the DRAM expected to be equal to ...
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DDR1 and DDR2 SDRAM Table 16 provides the DDR capacitance when GV Table 16. DDR SDRAM Capacitance for GV Parameter Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Note: 1 This parameter is sampled Table 17 provides ...
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Table 20 provides the input AC timing specifications for the DDR1 and DDR2 SDRAM interface. Table 20. DDR1 and DDR2 SDRAM Input AC Timing Specifications Parameter Controller skew for MDQS-MDQ/MECC/MDM 400 MHz data rate 333 MHz data rate 266 MHz ...
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DDR1 and DDR2 SDRAM Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued) Parameter MDQ//MDM output setup with respect to MDQS 400 MHz data rate 333 MHz data rate 266 MHz data rate 200 MHz data rate MDQ//MDM ...
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Figure 4 shows the DDR1 and DDR2 SDRAM output timing for the MCK to MDQS skew measurement (t ). DDKHMH Figure 5 shows the DDR1 and DDR2 SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 MDQS[n] MDQ[x] Figure 5. ...
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DUART Figure 6 provides the AC test load for the DDR bus. Output 7 DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8377E. 7.1 DUART DC Electrical Characteristics Table 22 provides the ...
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC) This section provides the AC and DC electrical characteristics for the enhanced three-speed Ethernet controller. 8.1 Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1000 Mbps)—MII/RGMII/RTBI/RMII DC Electrical Characteristics The electrical characteristics specified here apply to media ...
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC) Table 25. RGMII and RTBI DC Electrical Characteristics Parameter Supply voltage 2.5 V Output high voltage (LV /LV = Min, IOH = –1.0 mA) DD1 DD2 Output low voltage (LV /LV = Min ...
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The symbols used for timing specifications herein follow the pattern of t for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) transmit timing (MT) for the time t MTX general, the clock reference symbol representation is based on ...
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC) Figure 8 provides the AC test load for eTSEC. Output Figure 9 shows the MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER 8.2.2 RGMII and RTBI AC Timing Table 28 presents the RGMII and ...
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Table 28. RGMII and RTBI AC Timing Specifications (continued) At recommended operating conditions with LV Parameter/Condition EC_GTX_CLK125 reference clock period EC_GTX_CLK125 reference clock duty cycle measured at 0.5 × LV DD1 Note: 1 Note that, in general, the clock reference ...
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC) Figure 11 shows the RGMII and RTBI AC timing and multiplexing diagrams. GTX_CLK (At Transmitter) TXD[8:5][3:0] TXD[7:4][3:0] TX_CTL TX_CLK (At PHY) RXD[8:5][3:0] RXD[7:4][3:0] RX_CTL RX_CLK (At PHY) Figure 11. RGMII and RTBI AC Timing and ...
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Table 29. RMII Transmit AC Timing Specifications (continued) At recommended operating conditions with LV Parameter Fall time REF_CLK (80%–20%) REF_CLK to RMII data TXD[1:0], TX_EN delay Note: 1 The symbols used for timing specifications herein follow the pattern of t ...
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Ethernet: Enhanced Three-Speed Ethernet (eTSEC) Table 30. RMII Receive AC Timing Specifications (continued) At recommended operating conditions with LV Parameter/Condition RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge Note: 1 ...
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MII Management DC Electrical Characteristics The MDC and MDIO are defined to operate at a supply voltage of 2 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 31. MII Management DC ...
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USB Table 33. MII Management AC Timing Specifications (continued) Parameter MDC rise time (20%–80%) MDC fall time (80%–20%) Note: 1 The symbols used for timing specifications herein follow the pattern of t for inputs and t (first two letters of ...
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USB DC Electrical Characteristics Table 34 provides the DC electrical characteristics for the ULPI interface at recommended OV = 3.3 V ± 165 mV. DD Parameter High-level input voltage Low-level input voltage Input current = –100 μA High-level output ...
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Local Bus Figure 17 and Figure 18 provide the AC test load and signals for the USB, respectively. Output USBDR_CLK Input Signals t USKHOV Output Signals 10 Local Bus This section describes the DC and AC electrical specifications for the ...
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Table 37. Local Bus DC Electrical Characteristics (LBV At recommended operating conditions with LBV Parameter Supply voltage 2.5 V Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Table 38. Local ...
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Local Bus Table 39. Local Bus General Timing Parameters—PLL Enable Mode (continued) Parameter Local bus clock to output high impedance for LAD/LDP Output hold from local bus clock for LAD/LDP Note: 1 The symbols used for timing specifications herein follow ...
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Table 40 describes the general timing parameters of the local bus interface of the device when in PLL bypass mode. Table 40. Local Bus General Timing Parameters—PLL Bypass Mode Parameter Local bus cycle time Input setup to local bus clock ...
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Local Bus Figure 20 through Figure 25 show the local bus signals. LSYNC_IN Input Signals: LAD[0:31]/LDP[0:3] Input Signal: LGTA Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 20. Local Bus Signals, Non-special Signals ...
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LCLK[n] Input Signals: LAD[0:31] Input Signal: LGTA Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 21. Local Bus Signals, Non-special Signals Only (PLL Bypass Mode) MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. ...
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Local Bus LSYNC_IN T1 T3 GPCM Mode Output Signals: LCS[0:7]/LWE[0:3] UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:1]/LGPL[0:5] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] ...
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LCLK T1 T3 GPCM Mode Output Signals: LCS[0:7]/LWE[0:3] UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:1]/LGPL[0:5] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV ...
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Local Bus LSYNC_IN GPCM Mode Output Signals: LCS[0:7]/LWE[0:3] UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31] UPM Mode Output Signals: LCS[0:7]/LBS[0:1]/LGPL[0:5] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] Figure 24. Local Bus Signals, GPCM/UPM Signals ...
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LCLK GPCM Mode Output Signals: LCS[0:7]/LWE[0:3] UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31] UPM Mode Output Signals: LCS[0:7]/LBS[0:1]/LGPL[0:5] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] ...
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Enhanced Secure Digital Host Controller (eSDHC) Due to the special implementation of the eSDHC, there are constraints regarding the clock and data signals propagation delay on the user board. The constraints are for minimum and maximum delays, as well as ...
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Table 42. eSDHC AC Timing Specifications for Full-Speed Mode (continued) At recommended operating conditions OV Parameter Input hold times: SD_CMD, SD_DAT x , SD_CD to SD_CLK SD_CLK delay within device Output valid: SD_CLK to SD_CMD, SD_DAT x valid Output hold: ...
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Enhanced Secure Digital Host Controller (eSDHC) 11.2.1 Full-Speed Output Path (Write) Figure 27 provides the data and command output timing diagram. SD CLK at the MPC8377E Pin SD CLK at the Card Pin Output Valid Time: t Output Hold Time: ...
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CLK_DELAY This means that clock can be delayed versus data (external delay line) in ideal case ns: SFSCLKL < – CLK_DELAY t < 15 ...
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Enhanced Secure Digital Host Controller (eSDHC) 11.2.2.2 Full-Speed Read Meeting Hold (Minimum Delay) There is no minimum delay constraint due to the full clock cycle between the driving and sampling of data. t CLK_DELAY This means that Data + Clock ...
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Table 43. eSDHC AC Timing Specifications for High-Speed Mode (continued) At recommended operating conditions OV Parameter SD Card Output Hold Note: 1 The symbols used for timing specifications herein follow the pattern of t for inputs and t (reference)(state) (first ...
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Enhanced Secure Digital Host Controller (eSDHC) 11.3.1 High-Speed Output Path (Write) Figure 30 provides the data and command output timing diagram. SD CLK at the MPC8377E Pin SD CLK at the Card Pin Output Valid Time: t Output Hold Time: ...
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High-Speed Write Meeting Hold (Minimum Delay) The following equations show how to calculate the allowed skew range between the SD_CLK and SD_DAT/CMD signals on the PCB. t CLK_DELAY t CLK_DELAY This means that clock can be delayed versus data ...
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JTAG 11.3.2.1 High-Speed Read Meeting Setup (Maximum Delay) The following equations show how to calculate the allowed combined propagation delay range of the SD_CLK and SD_DAT/CMD signals on the PCB. t CLK_DELAY t CLK_DELAY This means that Data + Clock ...
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JTAG DC Electrical Characteristics Table 44 provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface of the MPC8377E. Table 44. JTAG interface DC Electrical Characteristics Parameter Input high voltage Input low voltage Input current Output high voltage ...
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JTAG Table 45. JTAG AC Timing Specifications (Independent of CLKIN) Parameter JTAG external clock to output high impedance: Boundary-scan data Notes: 1 All outputs are measured from the midpoint voltage of the falling/rising edge of t The output timings are ...
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Figure 35 provides the boundary-scan timing diagram. JTAG External Clock Boundary Data Inputs t JTKLDX Boundary Data Outputs Boundary Output Data Valid Data Outputs Figure 36 provides the test access port timing diagram. JTAG External Clock TDI, TMS t JTKLOX ...
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This section describes the DC and AC electrical characteristics for the Electrical Characteristics Table 46 provides the DC electrical characteristics for the I At recommended operating conditions ...
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Table 47. I All values refer to V (min) and V (max) levels (see IH IL Parameter Data hold time Setup time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level ...
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PCI 14 PCI This section describes the DC and AC electrical specifications for the PCI bus of the MPC8377E. 14.1 PCI DC Electrical Characteristics Table 48 provides the DC electrical characteristics for the PCI interface of the device. The DC ...
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Table 49. PCI AC Timing Specifications at 66 MHz (continued) PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1 × OV Parameter Input hold from Clock Output Clock Skew Notes: 1 Note that the symbols used for timing ...
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PCI Express Figure 39 provides the AC test load for PCI. Output Figure 40 shows the PCI input AC timing conditions. CLK Input Figure 40. PCI Input AC Timing Measurement Conditions Figure 41 shows the PCI output AC timing conditions. ...
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AC Requirements for PCI Express SerDes Clocks Table 51 lists the PCI Express SerDes clock AC requirements. Table 51. SD_REF_CLK and SD_REF_CLK AC Requirements Parameter REFCLK cycle time REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent ...
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PCI Express 15.4.1 Differential Transmitter (Tx) Output Table 52 defines the specifications for the differential output at all transmitters. The parameters are specified at the component pins. Table 52. Differential Transmitter (Tx) Output Specifications Parameter Conditions Unit interval Each U ...
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Table 52. Differential Transmitter (Tx) Output Specifications (continued) Parameter Conditions Absolute delta TX-CM-DC-D+ ≤ common mode between D+ and D– V TX-CM-DC- TX-D+ V TX-CM-DC- TX-D- Electrical idle ...
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PCI Express Table 52. Differential Transmitter (Tx) Output Specifications (continued) Parameter Conditions Common mode return Measured over 50 MHz to loss 1.25 GHz. DC differential differential mode low impedance impedance Transmitter DC Required well ...
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The exact reduced voltage level of the de-emphasized bit is always relative to the transition bit. The eye diagram must be valid for any 250 consecutive UIs. A recovered calculated over ...
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PCI Express Table 53. Differential Receiver (Rx) Input Specifications (continued) Parameter Minimum receiver eye The maximum interconnect width media and transmitter jitter that can be tolerated by the receiver can be derived as T RX-MAX-JITTER U = 0.6 UI. PEEWRX ...
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Table 53. Differential Receiver (Rx) Input Specifications (continued) Parameter Unexpected Electrical Idle An unexpected electrical idle Enter Detect Threshold (Vrx-diffp-p < Integration Time Vrx-idle-det-diffp-p) must be recognized no longer than Trx-idle-det-diff-entertime to signal an unexpected idle condition. Total Skew Skew ...
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PCI Express parasitic characteristics that cause the real PCI Express component to vary in impedance from the compliance/test measurement load. The input receiver eye diagram is implementation specific and is not specified. Rx component designer should provide additional margin to ...
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Compliance Test and Measurement Load The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in The allowance of the measurement point ...
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Serial ATA (SATA) Table 54. SATA Reference Clock Input Requirements (continued) Parameter SD_REF_CLK/ SD_REF_CLK cycle to cycle Clock jitter (period jitter) SD_REF_CLK/ SD_REF_CLK total reference clock jitter, phase jitter (peak-peak) Note: 1 Only 100/125/150 MHz have been tested, othe in ...
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Table 56 provides the differential transmitter output AC characteristics for the SATA interface at Gen1i or 1.5 Gbits/s transmission. Table 56. Gen1i/1.5G Transmitter AC Specifications Parameter Channel speed Unit interval Total jitter, data-data 5 UI Total jitter, data-data 250 UI ...
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Serial ATA (SATA) Table 58. Gen 2i/3G Transmitter AC Specifications (continued) Parameter Total jitter /1667 C3dB BAUD Deterministic jitter /10 C3dB BAUD Deterministic jitter /500 C3dB BAUD Deterministic jitter f = ...
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Table 60. Gen 1i/1.5G Receiver AC Specifications (continued) Parameter Deterministic jitter, data-data 250 UI Note: 1 Measured at Tx output pins peak to peak phase variation, random data pattern. 16.3.2 Gen2i/3G Receiver (Rx) Specifications Table 61 provides the Gen2i or ...
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Timers 17 Timers This section describes the DC and AC electrical specifications for the timers of the MPC8377E. 17.1 Timers DC Electrical Characteristics Table 63 provides the DC electrical characteristics for the device timers pins, including TIN, TOUT, TGATE, and ...
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GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8377E. 18.1 GPIO DC Electrical Characteristics Table 65 provides the DC electrical characteristics for the device GPIO. Table 65. GPIO DC Electrical Characteristics This ...
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SPI 19.1 IPIC DC Electrical Characteristics Table 67 provides the DC electrical characteristics for the external interrupt pins of the MPC8377E. Parameter Input high voltage Input low voltage Input current Output low voltage Output low voltage Note: 1. This table ...
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Table 69. SPI DC Electrical Characteristics (continued) Parameter Output low voltage Output low voltage 20.2 SPI AC Timing Specifications Table 70 provides the SPI input and output AC timing specifications. Parameter SPI outputs—Master mode (internal clock) delay SPI outputs—Slave mode ...
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High-Speed Serial Interfaces (HSSI) Figure 49 shows the SPI timing in slave mode (external clock). SPICLK (input) t NEIVKH Input Signals: SPIMOSI (See Note) Output Signals: SPIMISO (See Note) Note: The clock edge is selectable on SPI. Figure 49. SPI ...
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Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment. • Single-Ended Swing The transmitter output signals and the receiver input ...
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High-Speed Serial Interfaces (HSSI _TX _RX A Volts SD n _TX _RX B Volts Figure 51. Differential Voltage Definitions for Transmitter or Receiver To illustrate these definitions using real values, consider the ...
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The SerDes reference clock input can be either differential or single-ended. Refer to the Differential Mode and Single-ended Mode description below for further detailed requirements. • The maximum average current requirement that also determines the common mode voltage range ...
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High-Speed Serial Interfaces (HSSI) greater than 200 mV. This requirement is the same for both external DC-coupled or AC-coupled connection. — For external DC-coupled connection, as described in Clock Receiver Characteristics,” the maximum average current requirements sets the requirement for ...
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Input Amplitude or Differential Peak < 800 _REF_CLK SD n _REF_CLK Figure 54. Differential Reference Clock Input DC Requirements (External AC-Coupled _REF_CLK SD n _REF_CLK Figure 55. Single-Ended Reference Clock Input DC ...
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High-Speed Serial Interfaces (HSSI) Figure 56 to Figure 59 fact that clock driver chip's internal structure, output impedance, and termination requirements are different between various clock driver chip manufacturers very possible that the clock circuit reference designs provided ...
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It also assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external component. LVDS CLK Driver Chip 10 nF CLK_Out Clock Driver Clock Driver ...
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High-Speed Serial Interfaces (HSSI) clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip. LVPECL CLK Driver Chip CLK_Out R1 Clock Driver Clock Driver CLK_Out R1 Figure 58. AC-Coupled Differential Connection with ...
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MHz range. The source impedance of the clock driver should be 50 Ω to match the transmission line and reduce reflections which are a source of noise to the system. Table 71 describes some AC parameters ...
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Package and Pin Listings 21.3 SerDes Transmitter and Receiver Reference Circuits Figure 62 shows the reference circuits for SerDes data lane’s transmitter and receiver. Transmitter Figure 62. SerDes Transmitter and Receiver Reference Circuits The DC and AC specification of SerDes ...
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Figure 63 shows the mechanical dimensions and bottom surface nomenclature of the TEPBGA II package. Figure 63. Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II Note: 1 All dimensions are in millimeters. 2 Dimensioning and tolerancing per ASME ...
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Package and Pin Listings 4 Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5 Parallelism measurement should exclude any effect of mark on top surface of package. 22.2 Pinout Listings Table 72 provides ...
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Table 72. TePBGA II Pinout Listing (continued) Signal MBA2 MCAS_B MCK_B0 MCK_B1 MCK_B2 MCK_B3 MCK_B4 MCK_B5 MCK0 MCK1 MCK2 MCK3 MCK4 MCK5 MCKE0 MCKE1 MCS_B0 MCS_B1 MCS_B2 MCS_B3 MDIC0 MDIC1 MDM0 MDM1 MDM2 MDM3 MDM4 MDM5 MDM6 MDM7 MDM8 MDQ0 ...
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Package and Pin Listings Table 72. TePBGA II Pinout Listing (continued) Signal MDQ2 MDQ3 MDQ4 MDQ5 MDQ6 MDQ7 MDQ8 MDQ9 MDQ10 MDQ11 MDQ12 MDQ13 MDQ14 MDQ15 MDQ16 MDQ17 MDQ18 MDQ19 MDQ20 MDQ21 MDQ22 MDQ23 MDQ24 MDQ25 MDQ26 MDQ27 MDQ28 MDQ29 ...
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Table 72. TePBGA II Pinout Listing (continued) Signal MDQ35 MDQ36 MDQ37 MDQ38 MDQ39 MDQ40 MDQ41 MDQ42 MDQ43 MDQ44 MDQ45 MDQ46 MDQ47 MDQ48 MDQ49 MDQ50 MDQ51 MDQ52 MDQ53 MDQ54 MDQ55 MDQ56 MDQ57 MDQ58 MDQ59 MDQ60 MDQ61 MDQ62 MDQ63 MDQS0 MDQS1 MDQS2 ...
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Package and Pin Listings Table 72. TePBGA II Pinout Listing (continued) Signal MDQS4 MDQS5 MDQS6 MDQS7 MDQS8 MECC0/MSRCID0 MECC1/MSRCID1 MECC2/MSRCID2 MECC3/MSRCID3 MECC4/MSRCID4 MECC5/MDVAL MECC6 MECC7 MODT0 MODT1 MODT2 MODT3 MRAS_B MVREF1 MVREF2 MWE_B UART_SIN1/ MSRCID2/LSRCID2 UART_SOUT1/ MSRCID0/LSRCID0 UART_CTS_B[1]/ MSRCID4/LSRCID4 UART_RTS_B1 ...
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Table 72. TePBGA II Pinout Listing (continued) Signal UART_RTS_B[2] LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LA11/LAD16 LA12/LAD17 LA13/LAD18 LA14/LAD19 LA15/LAD20 LA16/LAD21 LA17/LAD22 LA18/LAD23 LA19/LAD24 LA20/LAD25 LA21/LAD26 LA22/LAD27 LA23/LAD28 LA24/LAD29 MPC8377E ...
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Package and Pin Listings Table 72. TePBGA II Pinout Listing (continued) Signal LA25/LAD30 LA26/LAD31 LA27 LA28 LA29 LA30 LA31 LA10/LALE LBCTL LCLK0 LCLK1 LCLK2 LCS_B0 LCS_B1 LCS_B2 LCS_B3 LCS_B4/LDP0 LCS_B5/LDP1 LA7/LCS_B6/LDP2 LA8/LCS_B7/LDP3 LFCLE/LGPL0 LFALE/LGPL1 LFRE_B/LGPL2/LOE_B LFWP_B/LGPL3 LGPL4/LFRB_B/LGTA_B/ LUPWAIT/LPBSE LA9/LGPL5 LSYNC_IN ...
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Table 72. TePBGA II Pinout Listing (continued) Signal TSEC1_COL/GPIO2[20] TSEC1_CRS/GPIO2[21] TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RX_ER/GPIO2[25] TSEC1_RXD0 TSEC1_RXD1 TSEC1_RXD2 TSEC1_RXD3 TSEC1_TX_CLK TSEC1_TX_EN TSEC1_TX_ER/CFG_LBMUX TSEC1_TXD0/ CFG_RESET_SOURCE[0] TSEC1_TXD1/ CFG_RESET_SOURCE[1] TSEC1_TXD2/ CFG_RESET_SOURCE[2] TSEC1_TXD3/ CFG_RESET_SOURCE[3] EC_GTX_CLK125 EC_MDC/CFG_CLKIN_DIV EC_MDIO TSEC2_COL/GPIO1[21]/ TSEC1_TMR_TRIG1 TSEC2_CRS/GPIO1[22]/ TSEC1_TMR_TRIG2 TSEC2_GTX_CLK TSEC2_RX_CLK/ TSEC1_TMR_CLK TSEC2_RX_DV/GPIO1[23] ...
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Package and Pin Listings Table 72. TePBGA II Pinout Listing (continued) Signal TSEC2_RXD0/GPIO1[16] TSEC2_RXD1/GPIO1[15] TSEC2_RXD2/GPIO1[14] TSEC2_RXD3/GPIO1[13] TSEC2_TX_CLK/GPIO2[24]/ TSEC1_TMR_GCLK TSEC2_TX_EN/GPIO1[12]/ TSEC1_TMR_ALARM2 TSEC2_TX_ER/GPIO1[24]/ TSEC1_TMR_ALARM1 TSEC2_TXD0/GPIO1[20] TSEC2_TXD1/GPIO1[19]/ TSEC1_TMR_PP1 TSEC2_TXD2/GPIO1[18]/ TSEC1_TMR_PP2 TSEC2_TXD3/GPIO1[17]/ TSEC1_TMR_PP3 GPIO1[0]/GTM1_TIN1/ GTM2_TIN2/DREQ0_B GPIO1[1]/GTM1_TGATE1_B/ GTM2_TGATE2_B/DACK0_B GPIO1[2]/GTM1_TOUT1_B/ DDONE0_B GPIO1[3]/GTM1_TIN2/ GTM2_TIN1/DREQ1_B GPIO1[4]/GTM1_TGATE2_B/ GTM2_TGATE1_B/DACK1_B GPIO1[5]/GTM1_TOUT2_B/ ...
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Table 72. TePBGA II Pinout Listing (continued) Signal GPIO1[10]/GTM1_TGATE4_B/ GTM2_TGATE3_B/DACK3_B GPIO1[11]/GTM1_TOUT4_B/ GTM2_TOUT3_B/DDONE3_B USBDR_CLK/GPIO2[23] USBDR_DIR_DPPULLUP/ GPIO2[9] USBDR_NXT/GPIO2[8] USBDR_PCTL0/GPIO2[11]/ SD_DAT2 USBDR_PCTL1/GPIO2[22]/ SD_DAT3 USBDR_PWRFAULT/ GPIO2[10]/SD_DAT1 USBDR_STP_SUSPEND USBDR_D0_ENABLEN/ GPIO2[0] USBDR_D1_SER_TXD/ GPIO2[1] USBDR_D2_VMO_SE0/ GPIO2[2] USBDR_D3_SPEED/GPIO2[3] USBDR_D4_DP/GPIO2[4] USBDR_D5_DM/GPIO2[5] USBDR_D6_SER_RCV/ GPIO2[6] USBDR_D7_DRVVBUS/ GPIO2[7] IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA ...
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Package and Pin Listings Table 72. TePBGA II Pinout Listing (continued) Signal TDI TDO TMS TRST_B PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 ...
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Table 72. TePBGA II Pinout Listing (continued) Signal PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_C_BE_B0 PCI_C_BE_B1 PCI_C_BE_B2 PCI_C_BE_B3 PCI_DEVSEL_B PCI_FRAME_B PCI_GNT_B0 PCI_GNT_B[1]/ CPCI_HS_LED PCI_GNT_B[2]/ CPCI_HS_ENUM PCI_GNT_B[3]/PCI_PME PCI_GNT_B[4] PCI_IDSEL PCI_INTA_B/IRQ_OUT_B PCI_IRDY_B PCI_PAR PCI_PERR_B PCI_REQ_B0 PCI_REQ_B[1]/CPCI_HS_ES PCI_REQ_B2 PCI_REQ_B3 PCI_REQ_B4 PCI_RESET_OUT_B PCI_SERR_B PCI_STOP_B PCI_TRDY_B ...
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Package and Pin Listings Table 72. TePBGA II Pinout Listing (continued) Signal Programmable Interrupt Controller (PIC) Interface MCP_OUT_B IRQ_B0/MCP_IN_B/GPIO2[12] IRQ_B1/GPIO2[13] IRQ_B2/GPIO2[14] IRQ_B3/GPIO2[15] IRQ_B4/GPIO2[16] IRQ_B5/GPIO2[17]/ USBDR_PWRFAULT IRQ_B6/GPIO2[18] IRQ_B7/GPIO2[19] QUIESCE_B L1_SD_IMP_CAL_RX L1_SD_IMP_CAL_TX L1_SD_REF_CLK L1_SD_REF_CLK_B L1_SD_RXA_N L1_SD_RXA_P L1_SD_RXE_N L1_SD_RXE_P L1_SD_TXA_N L1_SD_TXA_P L1_SD_TXE_N L1_SD_TXE_P ...
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Table 72. TePBGA II Pinout Listing (continued) Signal L1_XCOREVSS AG14, AG15, AG16, AH16, AG18, AG20 L1_XPADVDD L1_XPADVSS L2_SD_IMP_CAL_RX L2_SD_IMP_CAL_TX L2_SD_REF_CLK L2_SD_REF_CLK_B L2_SD_RXA_N L2_SD_RXA_P L2_SD_RXE_N L2_SD_RXE_P L2_SD_TXA_N L2_SD_TXA_P L2_SD_TXE_N L2_SD_TXE_P L2_SDAVDD_0 L2_SDAVSS_0 L2_XCOREVDD L2_XCOREVSS L2_XPADVDD L2_XPADVSS SPICLK/SD_CLK MPC8377E PowerQUICC II Pro ...
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Package and Pin Listings Table 72. TePBGA II Pinout Listing (continued) Signal SPIMISO/SD_DAT0 SPIMOSI/SD_CMD SPISEL_B/SD_CD SRESET_B HRESET_B PORESET_B TEST Reserved LVDD1 LVDD2 LBVDD VDD K10, L10, M10, N10, P10, R10, T10, U10, V10, W10, Y10, K11, R11, Y11, K12, Y12, ...
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Table 72. TePBGA II Pinout Listing (continued) Signal GND A1, AJ1, H2, N2, AA2, AD2, D3, R3, AF3, A4, F4, J4, L4, V4, Y4, AB4, B5, E5, P5, AH5, K6, (VSS) T6, AA6, AD6, AG6, F7, J7, Y7, AJ7, B8, ...
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Package and Pin Listings Table 72. TePBGA II Pinout Listing (continued) Signal Pull Down Note: 1 This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD. 2 This pin ...
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Clocking Figure 64 shows the internal distribution of clocks within the MPC8377E. System PLL CFG_CLKIN_DIV CLKIN The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured ...
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Clocking As shown in Figure 64, the primary clock input (frequency) is multiplied up by the system phase-locked loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the DDR controller (ddr_clk), ...
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Table 73. Configurable Clock Units (continued) Unit PCI Express1, 2 SATA1 This only applies clock is not configurable). Table 74 provides the operating frequencies for the TePBGA II package under recommended ...
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Clocking 23.1 System PLL Configuration The system PLL is controlled by the RCWL[SPMF] parameter. The system PLL VCO frequency depends on RCWL[DDRCM] and RCWL[LBCM]. system PLL. If RCWL[DDRCM] and RCWL[LBCM] are both cleared, the system PLL VCO frequency = (CSB ...
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Table 77. CSB Frequency Options for Host Mode CFG_CLKIN_DIV SPMF 1 at Reset High 0010 High 0011 High 0100 High 0101 High 0110 High 0111 High 1000 High 1001 High 1010 High 1011 High 1100 High 1101 High 1110 High ...
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Clocking Table 78. CSB Frequency Options for Agent Mode (continued) CFG_CLKIN_DIV SPMF 1 at reset Low 0111 Low 1000 Low 1001 Low 1010 Low 1011 Low 1100 Low 1101 Low 1110 Low 1111 1 CFG_CLKIN_DIV doubles csb_clk if set high. ...
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Table 79. e300 Core PLL Configuration (continued) RCWL[COREPLL] 0–1 2–5 10 0001 00 0010 01 0010 10 0010 00 0010 01 0010 10 0010 00 0011 01 0011 10 0011 00 0011 01 0011 10 0011 00 0100 01 0100 ...
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Thermal Table 80. Example Clock Frequency Combinations (continued) 1 Ref LBCM DDRCM SVCOD SPMF 66.7 0 ...
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Table 81. Package Thermal Characteristics for TePBGA II (continued) Parameter Junction-to-package natural convection on top Note: 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power ...
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Thermal The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies ...
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The thermal resistance is expressed as the sum of a junction to case thermal resistance and a case-to-ambient thermal resistance θ θ where junction to ambient thermal resistance (°C/W) θ ...
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Thermal Table 82 shows the heat sink thermal resistance for TePBGA II package with heat sinks, simulated in a standard JEDEC environment, per JESD 51-6. Table 82. Thermal Resistance with Heat Sink in Open Flow (TePBGA II) Heat Sink Assuming ...
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Tyco Electronics Chip Coolers™ www.chipcoolers.com Wakefield Engineering www.wakefield.com Interface material vendors include the following: Chomerics, Inc. www.chomerics.com Dow-Corning Corporation Dow-Corning Electronic Materials www.dowcorning.com Shin-Etsu MicroSi, Inc. www.microsi.com The Bergquist Company www.bergquistcompany.com 24.3 Heat Sink Attachment The device requires the use ...
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System Design Information R = junction to case thermal resistance (°C/W) θ power dissipation ( System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC8377E. 25.1 PLL Power ...
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These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition recommended that there be several bulk ...
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Ordering Information The value of this resistance and the strength of the driver’s current source can be found by making two measurements. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured ...
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... VR = Pb-free a 125° 689 TePBGA –40° 125° for more information on the available package type. MPC8378E 800 MHz/400 MHz 667 MHz/400 MHz 533 MHz/333 MHz 400 MHz/266 MHz Ordering Information e300 core DDR Revision 3 Frequency ...
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... SVR and PVR settings by device. Table 86. SVR and PVR Settings by Product Revision Device Package MPC8377 MPC8377E MPC8378 TePBGA II MPC8378E MPC8379 MPC8379E 26.2 Part Marking Parts are marked as in the example shown in Figure 67. Freescale Part Marking for TePBGA II Devices MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3 ...
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Document Revision History Table 87 provides a revision history for this hardware specification. Revision Date 3 03/2010 • Added Section 4.3, “eTSEC Gigabit Reference Clock Timing.” • In Table 34, “USB DC Electrical Mode Only),” added table footnotes . ...
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Document Revision History Table 87. Document Revision History (continued) Revision Date 1 02/2009 • In Table 3, “Recommended Operating Conditions,” added two new rows for 800 MHz, and created two rows for SerDes. In addition, changed 666 to 667 MHz. ...
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... Power.org. IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3au, 802.3ab, 1588 are registered trademarks of the Institute of Electrical and Electronics Engineers, Inc. (IEEE). This product is not endorsed or approved by the IEEE. All other product or service names are the property of their respective owners. © 2008–2010 Freescale Semiconductor, Inc. All rights reserved. ...