MSC8113 Freescale Semiconductor / Motorola, MSC8113 Datasheet
MSC8113
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MSC8113 Summary of contents
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... Flexible memory controller with three UPMs, a GPCM, a page-mode SDRAM machine, glueless interface to a variety of memories and devices, byte enables for 64- or 32-bit bus widths, © Freescale Semiconductor, Inc., 2008. All rights reserved. Document Number: MSC8113 MSC8113 FC-PBGA–431 20 mm × memory banks for external memories, and 2 memory banks for IPBus peripherals and internal memories ...
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... Ordering Information .41 5 Package Information .42 6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 List of Figures Figure 1. MSC8113 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3 ® Figure 2. StarCore SC140 DSP Extended Core Block Diagram . 3 Figure 3. MSC8113 Package, Top View Figure 4. MSC8113 Package, Bottom View . . . . . . . . . . . . . . . . . . 6 Figure 5. Overshoot/Undershoot Voltage for V Figure 6. Start-Up Sequence: V ...
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... Notes: 1. The arrows show the data transfer direction. 2. The QBus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines four QBus banks. In addition, the QBC handles internal memory contentions. Figure 2. StarCore MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor SC140 SC140 ...
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... Pin Assignments 1 Pin Assignments This section includes diagrams of the MSC8113 package ball grid array layouts and pinout allocation tables. 1.1 FC-PBGA Ball Layout Diagrams Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index numbers. ...
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... HD7 HD15 HD9 HD60 DDH HD14 HD12 HD10 HD63 HD59 DD AB GND HD13 HD11 HD8 HD62 HD61 MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor Top View GND GND GND GND ...
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... DDH HD34 HD37 GND DDH HD35 HD38 HD42 HD36 HD39 HD41 HD44 DD MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev Bottom View GND GND GND GND GND GND DD DD ...
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... C10 GND C11 V DD C12 GND C13 V DD C14 GND C15 GND C16 GPIO30/TIMER2/TMCLK/SDA C17 GPIO2/TIMER1/CHIP_ID2/IRQ6 MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor Des. Signal Name C18 GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1 C19 GPIO7/TDM3RCLK/IRQ5/ETHTXD3 C20 GPIO3/TDM3TSYN/IRQ1/ETHTXD2 C21 GPIO5/TDM3TDAT/IRQ3/ETHRXD3 C22 GPIO6/TDM3RSYN/IRQ4/ETHRXD2 D2 TDI D3 EE0 ...
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... ETHTX_CLK/ETHREF_CLK/ETHCLOCK F17 GPIO20/TDM1RDAT F18 GPIO18/TDM1RSYN/DREQ2 F19 GPIO16/TDM1TCLK/DONE1/DRACK1 F20 GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD F21 GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC F22 GPIO19/TDM1RCLK/DACK2 G2 HA24 G3 HA27 G4 HA25 G5 HA23 MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev Des. Signal Name G6 HA17 G7 PWE0/PSDDQM0/PBS0 G10 IRQ3/BADDR31 G11 BM0/TC0/BNKSEL0 G12 ABB/IRQ4 G13 ...
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... K6 PWE1/PSDDQM1/PBS1 K7 POE/PSDRAS/PGPL2 K8 IRQ2/BADDR30 K9 Reserved K10 GND K11 GND K12 GND K13 GND K14 CLKOUT MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor Des. Signal Name K15 V DD K16 TT2/CS5 K17 ALE K18 CS2 K19 GND K20 A26 K21 A29 ...
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... A20 P2 HD20 P3 HD27 P4 HD25 P5 HD23 P6 HWBS3/HDBS3/HWBE3/HDBE3 P7 HWBS2/HDBS2/HWBE2/HDBE2 P8 HWBS1/HDBS1/HWBE1/HDBE1 P9 HCLKIN P10 GND P11 GND SYN MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev Des. Signal Name P12 V CCSYN P13 GND P14 GND P15 TA P16 BR P17 TEA P18 PSDVAL P19 DP0/DREQ1/EXT_BR2 P20 ...
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... U12 D15 U13 D17 U14 D19 U15 D22 U16 D25 U17 D26 U18 D28 U19 D31 U20 V DDH MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor Des. Signal Name U21 A12 U22 A13 V2 HD3/MODCK1 V3 V DDH V4 GND ...
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... Y21 A4 Y22 A5 AA2 V DD AA3 HD14 AA4 HD12 AA5 HD10 AA6 HD63/D63 AA7 HD59/D59/ETHMDIO AA8 GND MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev Des. Signal Name AA9 V DDH AA10 HD54/D54/ETHTX_EN AA11 HD52/D52 AA12 V DDH AA13 GND AA14 V DDH AA15 ...
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... Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 2 describes the maximum electrical ratings for the MSC8113. Rating Core and PLL supply voltage ...
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... Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. Section 4.5, Thermal Considerations provides a detailed explanation of these characteristics. 2.4 DC Electrical Characteristics This section describes the DC electrical characteristics for the MSC8113. The measurements in Table 5 assume the following system conditions: • °C A • ...
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... MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601 17% DDH DDH V GND V IL GND – 0.3 V GND – 0.7 V Figure 5. Overshoot/Undershoot Voltage for V MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor Table 5. DC Electrical Characteristics Symbol IHC V ILC ...
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... The following figures show acceptable start-up sequence examples. Figure 6 shows a sequence in which raised together. Figure 7 shows a sequence in which 3.3 V 2.2 V 1.1 V o.5 V Figure 6. Start-Up Sequence: V MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev Table 6. Output Buffer Impedances and levels together. For designs with separate power supplies, bring up the V DDH ...
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... SC140 core clock frequency Note: The rise and fall time of external clocks should maximum Characteristic Phase jitter between BCLK and CLKIN CLKIN frequency CLKIN slope PLL input clock (after predivider) MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor V = Nominal DDH V = Nominal DD ...
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... Host reset command through JTAG All MSC8113 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 10 describes the reset sources. ...
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... Through the direct slave interface (DSI) • Through the system bus. When the reset configuration is written through the system bus, the MSC8113 acts as a configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is written, a default configuration word is applied. ...
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... Input PORESET Internal HRESET Output (I/O) SRESET Output (I/O) Figure 8. Timing Diagram for a Reset Configuration Write MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev CNFGS, DSISYNC, DSI64, RSTCONF , RSTCONF, CNFGS, DSISYNC, DSI64 CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2] pins are sampled Host programs ...
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... System Bus Access Timing 2.5.5.1 Core Data Transfers Generally, all MSC8113 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The REFCLK is the CLKIN signal. Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4 ...
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... Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings. 2. Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge. 3. Guaranteed by design. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev Table 14. AC Timing for SIU Inputs Characteristic 3 Ref = CLKIN at 1 ...
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... The maximum bus frequency depends on the mode: • In 60x-compatible mode connected to another MSC8113 device, the frequency is determined by adding the input and output longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on. ...
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... Data bus inputs—ECC and parity modes Address bus/TS /TT[0–4]/TC[0–2]/ TBST/TSZ[0–3]/GBL inputs Address bus/TT[0–4]/TC[0–2]/TBST/TSZ[0–3]/GBL outputs Memory controller/ALE outputs AACK/ABB/TS/DBG/BG/BR/DBB/CS outputs MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev REFCLK 11 PSDVAL/ABB/DBB inputs 12 ...
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... DONE hold time after the 50% level of the rising edge of REFCLK 41 DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge signal is synchronized with The DREQ according to the timings in Table 17. Figure 12 shows synchronous peripheral interaction. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor skew timing. Table 16. CLKOUT Skew CLKIN CLKOUT 20 Figure 11 ...
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... Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn. 2. This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design. 3. All values listed in this table are tested or guaranteed by design. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev REFCLK 37 DREQ ...
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... HTA released at logic 0 (DCR[HTAAD end of access; used with pull-down implementation. 4. HTA released at logic 1 (DCR[HTAAD end of access; used with pull-up implementation. Figure 13. Asynchronous Single- and Dual-Strobe Modes Read Timing Diagram MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 100 101 112 102 ...
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... HRDS 1 HDBSn 2 HWBSn HD[0–63] Notes: 1. Used for single-strobe mode access. 2. Used for dual-strobe mode access. Figure 15. Asynchronous Broadcast Write Timing Diagram MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev 100 112 201 106 108 100 112 201 202 101 102 ...
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... HCLKIN high to HTA output active 133 HCLKIN high to HTA output valid 134 HTA output hold time 135 HCLKIN high to HTA high impedance MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor Table 19. DSI Inputs in Synchronous Mode Characteristic Electrical Characteristics 1.1 V Core Expression ...
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... Devices operating at 300 MHz are limited to a maximum TDMxRCLK/TDMxTCLK frequency of 50 MHz. 2. Values are based capacitive load. 3. When configured as an output, TDMxRCLK acts as a second data link. See the MSC8113 Reference Manual for details. 4. Values are based capacitive load. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 ...
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... TDMxRCLK 303 TDMxRDAT 303 TDMxRSYN TDMxTCLK TDMxTDAT TDMxRCLK TDMxTSYN MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 300 301 302 304 304 Figure 17. TDM Inputs Signals 300 301 302 306 305 309 Figure 18. TDM Output Signals Electrical Characteristics 308 ...
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... TIMERx frequency 501 TIMERx Input high period 502 TIMERx Output low period 503 TIMERx Propagations delay from its clock input MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev Table 22. UART Timing 401 401 400 Figure 19. UART Input Timing 402 402 Figure 20 ...
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... Table 24. Ethernet Controller Management Interface Timing No. 801 ETHMDIO to ETHMDC rising edge set-up time 802 ETHMDC rising edge to ETHMDIO hold time ETHMDC ETHMDIO Figure 22. MDIO Timing Relationship to MDC MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 500 501 502 503 Figure 21. Timer Timing Characteristics 801 ...
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... ETHREF_CLK rising edge to ETHTXD[0–1], ETHTX_EN output delay. ETHREF_CLK ETHCRS_DV ETHRXD[0–1] ETHRX_ER ETHTX_EN ETHTXD[0–1] MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev Table 25. MII Mode Signal Timing Characteristics 803 Valid 805 Valid Figure 23. MII Mode Signal Timing Table 26 ...
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... GPIO in valid to REFCLK edge (GPIO in set-up time) 605 REFCLK edge to GPIO in not valid (GPIO in hold time) REFCLK 603 GPIO (Output) GPIO (Input) MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor Table 27. SMII Mode Signal Timing Characteristics 808 809 Valid 810 Valid Figure 25 ...
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... TRST assert time 713 TRST set-up time to TCK low Note: All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev Table 29. EE Pin Timing Type Asynchronous Synchronous to Core clock pins ...
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... TDI TMS (Input) TDO (Output) TDO (Output) Figure 30. Test Access Port Timing Diagram TCK (Input) TRST (Input) 712 MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 701 703 704 Input Data Valid 706 Output Data Valid ...
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... DDH 3.2 Power Supply Design Considerations When implementing a new design, use the guidelines described in the MSC8113 Design Checklist (AN3374 for optimal system performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937) provides detailed design information. Figure 32 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the decoupling capacitors should supply the required device current without any drop in voltage on the device pins ...
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... For best results, place this capacitor on the backside of the PCB aligned with the depopulated void on the MSC8113 located in the square defined by positions, L11, L12, L13, M11, M12, M13, N11, N12, and N13. ...
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... SDRAM) making sure that the delay path the CLKIN between the clock buffer to the MSC8113 and the SDRAM is equal (that is, has a skew less than 100 ps). — Valid clock modes in this scheme are 15, 19, 21, 23, 28, 29, 30, and 31. ...
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... I/O The power dissipation values for the MSC8113 are listed in Table 2-3. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes ...
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... MSC8113 Reference Manual (MSC8113RM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information. • Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8113 device. • SC140 DSP Core Reference Manual. Covers the SC3400 core architecture, control registers, clock registers, program control, and instruction set ...
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... Revision History Table 31 provides a revision history for this data sheet. Revision Date 0 Jun. 2007 • Initial public release. MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor Table 31. Document Revision History Description Revision History 43 ...
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... Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MSC8113 Rev. 0 5/2008 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...