VSP2260Y/2KC BURR-BROWN [Burr-Brown Corporation], VSP2260Y/2KC Datasheet
VSP2260Y/2KC
Related parts for VSP2260Y/2KC
VSP2260Y/2KC Summary of contents
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CCD SIGNAL PROCESSOR for DIGITAL CAMERAS FEATURES CCD SIGNAL PROCESSING: Correlated Double Sampling (CDS) Programmable Black Level Clamping PROGRAMMABLE GAIN AMPLIFIER (PGA): –6dB to +42dB Gain Ranging 10-BIT DIGITAL DATA OUTPUT 20MHz Conversion Rate No Missing Codes ...
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SPECIFICATIONS + +3.0V, DRV = +3.0V, Conversion Rate ( PARAMETER RESOLUTION CONVERSION RATE DIGITAL INPUT Logic Family Input Voltage LOW to HIGH Threshold Voltage (VT+) HIGH to LOW Threshold Voltage (VT–) ...
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ABSOLUTE MAXIMUM RATINGS Supply Voltage DRV ........................................................... +4. Supply-Voltage Differences: Among V ......................................... 0.1V CC Ground-Voltage Differences: Among GNDA .................................... 0.1V Digital Input Voltage ............................................................ –0.3 to +5.3V Analog Input Voltage .................................................. –0 ...
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PIN CONFIGURATION Top View REFP 38 REFN GNDA 41 GNDA RESET SLOAD 46 SDATA 47 48 SCLK 1 PIN DESCRIPTIONS (1) DESCRIPTION PIN NAME TYPE 1 NC ...
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CDS TIMING SPECIFICATIONS CCD Output N Signal SHP ( (1) SHD t INHIBIT ADCCK t HOLD N – – 10 B[9:0] SYMBOL t CKP t ADCCK HIGH/LOW Pulse Width ADC ...
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SERIAL INTERFACE TIMING SPECIFICATIONS t XS SLOAD t CKH SCLK SDATA MSB SYMBOL t CKP t Clock HIGH Pulse Width CKH t Clcok LOW Pulse Width CKL SLOAD to SCLK Setup Time ...
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THEORY OF OPERATION INTRODUCTION The VSP2260 is a complete mixed-signal IC that contains all of the key features associated with the processing of the CCD imager output signal in a video camera, a digital still camera, security camera, or similar ...
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Reference, pin 39), and CM (Common-Mode Voltage, pin 37) should be bypassed to ground with a 0.1 F ceramic capacitor and should not be used elsewhere in the system, as they affect the stability of these reference levels, which ...
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ADCCK with a delay of nine clock cycles (data latency is nine). If the input voltage is higher than the supply rail by 0.3V, or lower than the ground rail by ...
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MSB REGISTERS TEST Configuration PGA Gain Clamp Level Clock Polarity Reserved Reserved ...
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TIMINGS The CDS and the ADC are operated by SHP/SHD and their derivative timing clocks generated by the on-chip timing generator. The digital output data is synchronized with ADCCK. See the VSP2260 “CDS Timing Specifications” for the timing relationship among ...
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... STATUS(1) VSP2260Y ACTIVE VSP2260Y/2K ACTIVE VSP2260Y/2KC ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ...
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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the ...