w25q64bv Winbond Electronics Corp America, w25q64bv Datasheet
w25q64bv
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w25q64bv Summary of contents
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... SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI Publication Release Date: March 13, 2009 - 1 - Preliminary - Revision B W25Q64BV ...
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... Status Register Protect (SRP1, SRP0) 10.1.7 Quad Enable (QE) 10.1.8 Status Register Memory Protection 10.2 INSTRUCTIONS 10.2.1 Manufacturer and Device Identification 10.2.2 Instruction Set Table 1 10.2.3 Instruction Set Table 2 (Read Instructions) Table of Contents ..........................................................................................................5 .......................................................................................6 ...................................................................................6 .......................................................................................7 .............................................................................................7 ................................................................................................................8 .............................................................................................................8 ..........................................................................................................8 ................................................................................................................8 ...........................................................................................................8 ..................................................................................................10 ........................................................................................................10 ...............................................................................................10 ......................................................................................................10 .....................................................................................................10 .................................................................................................................10 ..................................................................................................11 ....................................................................................................11 ...................................................................................12 .....................................................................................................12 ............................................................................................12 ..............................................................................12 .....................................................................................12 ..........................................................................................12 .........................................................................13 ........................................................................................................13 ..............................................................................15 ............................................................................................................16 ........................................................................16 .................................................................................................. W25Q64BV ........................................................6 ...............................8 ..................................................................18 ...
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... Serial Output Timing 11.9 Input Timing ...................................................................................................................52 11.10 Hold Timing ..................................................................................................................52 12. PACKAGE SPECIFICATION 12.1 8-Pin SOIC 208-mil (Package Code SS) ........................................................................................................19 .......................................................................................................19 ..........................................................................................21 ...........................................................................................................22 ...........................................................................................................23 .....................................................................................24 ....................................................................................25 ...........................................................................................26 .........................................................................................28 ...............................................................................30 ...................................................................................................32 ................................................................................33 .....................................................................................................34 .............................................................................................35 .............................................................................................36 ...............................................................................................37 ..................................................................................................38 ..................................................................................................38 ......................................................................................................39 ...................................................................................40 .........................................................................42 ............................................................................................43 ................................................................................................44 .........................................................................................46 ...........................................................................................46 .........................................................................................................46 ...............................................................47 .........................................................................................48 ........................................................................................49 .........................................................................................50 ............................................................................51 ......................................................................................................52 .....................................................................................................53 ...................................................................... W25Q64BV .................................20 .........................40 ..........................................................45 Publication Release Date: March 13, 2009 Preliminary - Revision B ...
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... WSON (Package Code ZE) 12.3 16-Pin SOIC 300-mil (Package Code SF) 13. ORDERING INFORMATION 13.1 Valid Part Numbers and Top Side Marking 14. REVISION HISTORY .................................................................................................................58 .............................................................54 .....................................................................55 .....................................................................................................56 ................................................................... W25Q64BV ...
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... Pages can be erased in groups of 16 (sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q64BV has 2,048 erasable sectors and 128 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage ...
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... PIN CONFIGURATION SOIC 208-MIL Figure 1a. W25Q64BV Pin Assignments, 8-pin SOIC 208-mil (Package Code SS) 4. PAD CONFIGURATION WSON 8X6-MM Figure 1b. W25Q64BV Pad Assignments, 8-pad WSON 8x6-mm(Package Code ZE) 5. PIN DESCRIPTION SOIC 208-MIL, AND WSON 6X5-MM PIN NO. PIN NAME 1 / (IO1) ...
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... PIN CONFIGURATION SOIC 300-MIL Figure 1c. W25Q64BV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 7. PIN DESCRIPTION SOIC 300-MIL PAD NO. PAD NAME 1 /HOLD (IO3) 2 VCC 3 N/C 4 N/C 5 N/C 6 N (IO1) 9 /WP (IO2) 10 GND 11 N/C 12 N/C 13 N (IO0) 16 CLK *1 IO0 and IO1 are used for Standard and Dual SPI instructions *2 IO0 – ...
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... Package Types W25Q64BV is offered in an 8-pin plastic 208-mil width SOIC (package code SS) and 8x6-mm WSON (package code ZE) as shown in figure 1a, and 1b, respectively. The W25Q64BV is also offered in a 16- pin plastic 300-mil width SOIC (package code SF) as shown in figure 1c. Package diagrams and dimensions are illustrated at the end of this datasheet. ...
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... SPI /CS /CS Command & Command & Control Logic Control Logic DI ( ( Figure 2. W25Q64BV Serial Flash Memory Block Diagram xxFFFFh xxFFFFh • • xxF0FFh xxF0FFh xxEFFFh xxEFFFh • • xxE0FFh xxE0FFh xxDFFFh xxDFFFh • • xxD0FFh xxD0FFh ...
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... Hold Function The /HOLD signal allows the W25Q64BV operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires use of the SPI bus ...
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... One Time Program (OTP) write protection Note 1: These features are available upon special order. Please contact Winbond for details. Upon power- power-down, the W25Q64BV will maintain a reset condition while VCC is below the threshold value (See Power-up Timing and Voltage Levels and Figure 31). While reset, all WI operations are disabled and no instructions are recognized ...
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... The non-volatile Sector protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0. , and Characteristics). When the program, erase or write status W25Q64BV ...
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... When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. Status Register is protected and can not be written to again (1) until the next power-down, power-up cycle. Status Register is permanently protected and can not be (1) written to. Publication Release Date: March 13, 2009 - 13 - W25Q64BV (2) Preliminary - Revision B ...
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... Figure 3a. Status Register-1 Figure 3b. Status Register W25Q64BV ...
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... X Note don’t care W25Q64BV (64M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES NONE NONE 126 & 127 7E0000h – 7FFFFFh 124 ~ 127 7C0000h – 7FFFFFh 120 ~ 127 780000h – 7FFFFFh 112 ~ 127 700000h – 7FFFFFh 96 ~ 127 600000h – ...
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... INSTRUCTIONS The instruction set of the W25Q64BV consists of twenty seven basic instructions that are fully controlled through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first ...
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... A23–A16 A15–A8 A23–A16 A15–A8 dummy dummy FFh dummy dummy dummy dummy dummy dummy (MF7-MF0) (ID15-ID8) Manufacturer Memory Type - 17 - W25Q64BV BYTE 4 BYTE 5 BYTE 6 A7–A0 (D7–D0) (3) A7–A0 (D7–D0, …) A7–A0 A7–A0 A7–A0 dummy (5) dummy (ID7-ID0) 00h (MF7-MF0) ...
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... IO3 = ( D7, D3, …..) 6. The lowest 4 address bits must A0, A1, A2 BYTE 2 BYTE 3 A23-A16 A15-A8 A23-A16 A15-A8 A23-A16 A15-A8 (2) (2) A23-A8 A7-A0, M7-M0 A23-A16 A15-A8 (4) A23-A0, M7-M0 (x,x,x,x, D7-D0, …) (4) (3) A23-A0, M7-M0 (D7-D0, … W25Q64BV BYTE 4 BYTE 5 A7-A0 (D7-D0) A7-A0 dummy A7-A0 dummy (1) (D7-D0, …) A7-A0 dummy (5) (3) (D7-D0, …) BYTE 6 (D7-D0) (1) (D7-D0, …) (3) (D7-D0, …) ...
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... DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase instructions. Figure 4. Write Enable Instruction Sequence Diagram Figure 5. Write Disable Instruction Sequence Diagram - 19 - W25Q64BV Publication Release Date: March 13, 2009 Preliminary - Revision B ...
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... Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 6. The instruction is completed by driving /CS high. Figure 6. Read Status Register Instruction Sequence Diagram - 20 - W25Q64BV ...
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... Write Protect (/WP) pin, Lock out or OTP features to disable writes to the status register. Please refer to 10.1.6 for detailed descriptions regarding Status Register protection methods. Factory default for all status Register bits are 0. Figure 7. Write Status Register Instruction Sequence Diagram (See AC Characteristics). W Publication Release Date: March 13, 2009 - 21 - W25Q64BV Preliminary - Revision B ...
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... The Read Data instruction sequence is shown in figure Read Data instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D. maximum of f (see AC Electrical Characteristics). Figure 8. Read Data Instruction Sequence Diagram - 22 - W25Q64BV R ...
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... The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is a “don’t care”. Figure 9. Fast Read Instruction Sequence Diagram - 23 - W25Q64BV Publication Release Date: March 13, 2009 Preliminary - Revision B ...
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... The input data during the dummy clocks is “don’t care”. However, the IO out clock. Figure 10. Fast Read Dual Output Instruction Sequence Diagram and IO . This allows data to be transferred from the W25Q64BV pin should be high-impedance prior to the falling edge of the first data 0 ...
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... IO be executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the W25Q64BV at four times the rate of standard SPI devices. ...
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... A “Continuous Read Mode” Reset instruction can be used to reset (M7-0) before issuing normal instructions (See 10.2.29 for detailed descriptions). Figure 12a. Fast Read Dual Input/Output Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh W25Q64BV ...
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... Figure 12b. Fast Read Dual Input/Output Instruction Sequence Diagram (M7-0 = Axh W25Q64BV Publication Release Date: March 13, 2009 Preliminary - Revision B ...
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... A “Continuous Read Mode” Reset instruction can be used to reset (M7-0) before issuing normal instructions (See 10.2.29 for detailed descriptions). Figure 13a. Fast Read Quad Input/Output Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh The Quad I/O dramatically reduces instruction overhead . - 28 - W25Q64BV and IO and four Dummy 2 3 Byte 1 Byte 1 Byte 2 Byte 2 ...
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... Figure 13b. Fast Read Quad Input/Output Instruction Sequence Diagram (M7-0 = Axh W25Q64BV Publication Release Date: March 13, 2009 Preliminary - Revision B ...
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... Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte W25Q64BV Byte 4 ...
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... Figure 14b. Octal Word Read Quad I/O Instruction Sequence (M7-0 = Axh W25Q64BV ...
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... After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits. Figure 15. Page Program Instruction Sequence Diagram - 32 - W25Q64BV ...
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... Quad Page Program are identical to standard Page Program. The Quad Page Program instruction sequence is shown in figure 16. Figure 16. Quad Input Page Program Instruction Sequence Diagram , and IO . The Quad Page Program can Publication Release Date: March 13, 2009 - 33 - W25Q64BV Preliminary - Revision B ...
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... Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). (See AC Characteristics). While the Sector Erase SE Figure 17. Sector Erase Instruction Sequence Diagram - 34 - W25Q64BV ...
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... Block Protect (SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 18. 32KB Block Erase Instruction Sequence Diagram 1 (See AC Characteristics). While the Block Erase BE Publication Release Date: March 13, 2009 - 35 - W25Q64BV Preliminary - Revision B ...
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... Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 19. 64KB Block Erase Instruction Sequence Diagram (See AC Characteristics). While the Block Erase cycle W25Q64BV ...
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... Status Register is cleared to 0. The Chip Erase instruction will not be executed if any section of the array is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory Protection table). (See AC Characteristics). While the Chip Erase cycle is in progress, CE Figure 20. Chip Erase Instruction Sequence Diagram - 37 - W25Q64BV Publication Release Date: March 13, 2009 Preliminary - Revision B ...
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... Erase Suspend. After issued the BUSY bit in the status register will be set and the sector or block will complete the erase operation. Resume instructions will be ignored unless an Erase Suspend operation is active. Figure 21. Erase Suspend Instruction Sequence Figure 22. Erase Resume Instruction Sequence - 38 - W25Q64BV ...
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... Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 23. Deep Power-down Instruction Sequence Diagram Publication Release Date: March 13, 2009 - 39 - W25Q64BV Preliminary - Revision B ...
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... The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 26. The Device ID values for the W25Q64BV is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. ...
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... Figure 25. Release Power-down/High Performance Mode Instruction Sequence Figure 26. Release Power-down / Device ID Instruction Sequence Diagram (See AC Characteristics). After this time duration the device will RES2 - 41 - W25Q64BV Publication Release Date: March 13, 2009 Preliminary - Revision B ...
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... Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 27. The Device ID values for the W25Q64BV is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
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... Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q64BV device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... Read JEDEC ID (9Fh) For compatibility reasons, the W25Q64BV provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...
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... If the system controller is Reset during operation it will likely send a standard SPI instruction, such as Read ID (9Fh) or Fast Read (0Bh), to the W25Q64BV. However, as with most SPI Serial Flash memories, the W25Q64BV does not have a hardware Reset pin Continuous Read Mode bits are set to “ ...
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... Electrostatic Discharge Voltage Notes: 1. Specification for W25Q64BV is preliminary. See preliminary designation at the end of this document. 2. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. ...
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... Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. SYMBOL MIN t (1) 10 VSL t (1) 1 PUW V 1 (1) WI Figure 31. Power-up Timing and Voltage Levels - 47 - W25Q64BV SPEC UNIT MAX µ Publication Release Date: March 13, 2009 Preliminary - Revision B ...
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... C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open /CS = VCC /CS = VCC /CS = VCC /CS = VCC –0.5 VCC –100 µA VCC – 0 W25Q64BV SPEC UNIT TYP MAX ±2 µA ±2 µ µ µA 50 100 µA 4/5/6 6/7 ...
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... Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. SYMBOL MIN 0.2 VCC to 0.8 VCC IN 0.3 VCC to 0.7 VCC IN O 0.5 VCC to 0.5 VCC UT Figure 32. AC Measurement I/O Waveform Publication Release Date: March 13, 2009 - 49 - W25Q64BV SPEC UNIT MAX Preliminary - Revision B ...
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... CHSH t 5 SHCH t t 10/50 SHSL CSH ( SHQZ DIS CLQV CLQV CLQX HLCH - 50 - W25Q64BV SPEC UNIT TYP MAX 80 MHz 50 MHz 50 MHz ns ns V/ns V/ 8 Continued – next page ...
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... SUS t W (4) t BP1 (4) t BP2 (typical) and BPN BP1 + BP2 * W25Q64BV SPEC ALT MIN TYP MAX 100 2 200 120 800 150 ...
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... Serial Output Timing 11.9 Input Timing 11.10 Hold Timing - 52 - W25Q64BV ...
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... Formed leads shall be planar with respect to one another within .0004 inches at the seating plane. MILLIMETERS INCHES MIN MAX MIN 1.75 2.16 0.069 0.05 0.25 0.002 1.70 1.91 0.067 0.35 0.48 0.014 0.19 0.25 0.007 5.18 5.38 0.204 7.70 8.10 0.303 5.18 5.38 0.204 1.27 BSC 0.050 BSC 0.50 0.80 0.020 --- 0.10 --- Publication Release Date: March 13, 2009 - 53 - W25Q64BV MAX 0.085 0.010 0.075 0.019 0.010 0.212 0.319 0.212 0.031 8 o 0.004 Preliminary - Revision B ...
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... BSC 0.45 0.50 0.55 0.0177 - 54 - W25Q64BV ( INCHES MIN TYP. MAX 0.0295 0.0315 0.0008 0.0019 0.0157 0.0189 0.0079 0.0098 0.3150 0.3189 0.1831 0.1850 0.2362 0.2402 0.2047 0.2067 0.0500 BSC 0.0197 0.0217 ...
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... Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. MILLIMETERS INCHES MIN MAX MIN 2.36 2.64 0.093 0.10 0.30 0.004 0.33 0.51 0.013 0.18 0.28 0.007 10.08 10.49 0.397 10.01 10.64 0.394 7.39 7.59 0.291 1.27 BSC 0.050 BSC 0.39 1.27 0.015 --- 0.076 --- Publication Release Date: March 13, 2009 - 55 - W25Q64BV MAX 0.104 0.012 0.020 0.011 0.413 0.419 0.299 0.050 8 o 0.003 Preliminary - Revision B ...
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... WSON package type ZE is not used for the part marking. 1b. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T), when placing orders. 1c. The “W” prefix is not included on the part marking. (1) W 25Q 8-pad WSON 8x6mm - 56 - W25Q64BV ( ...
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... Valid Part Numbers and Top Side Marking The following table provides the valid part numbers for the W25Q64BV SpiFlash Memory. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 11- digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 9-digit number ...
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... Winbond for any damages resulting from such improper use or sales. PAGE New Create Preliminary 56 & character added to end of a Part Number 57 Corrected Top Side Marking 5 Changed Active Current to 4mA 13 Typo Change QE pin to QE bit Important Notice - 58 - W25Q64BV DESCRIPTION ranteed. Winbond ...