w83601r

Manufacturer Part Numberw83601r
DescriptionWinbond Smbus Gpi/o
ManufacturerWinbond Electronics Corp America
w83601r datasheet
 


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W83601R/602R
Winbond SMBus GPI/O

w83601r Summary of contents

  • Page 1

    ... W83601R/602R Winbond SMBus GPI/O ...

  • Page 2

    ... Main Contents on Web n.a. All the version before 0.30 are for internal use. n.a. First publication. n.a. Change Pin Description of W83601R pin 3,4,5. Change Pin Description of W83602R pin 3,4. Update Register Table. CR16 is a reserved register. Please ignore it. Change INT output description. n.a. CR15 bit 3 description. Publication Release Date: Aug. 1999 ...

  • Page 3

    ... TM W83601R SMBus Address W83602R SMBus Address is : W83601R/602R also provides a interrupt to inform system that a transition occurs on General Purpose(GP) input pins. 2. FEATURES SMBus compliance with 3.3V voltage levels Two ports GPI/O which provides more flexibility Issue interrupt to notify system that a event occurs GP output can be level or pulse mode ...

  • Page 4

    ... KEY SPECIFICATIONS Supply Voltage Operating Supply Current Operating Temperature 5. PIN CONFIGURATION FOR W83601R/602R W83601R SCLK 1 20 SDAT 2 19 GP20/ GP21/ GP22/ GP10 6 15 GP11 7 14 GP23 8 13 GP24 9 12 VSS 10 11 20SSOP typ W83602R VDD SCLK ...

  • Page 5

    ... TTL level bi-directional pin with 24 mA source-sink capability TTL level input pin TTL level input pin with internal pull down resistor TTL level Schmitt-trigger input pin W83601R UNIVERSAL GENERAL PURPOSE I/O PORT FOR I2C BUS PIN SYMBOL I/O 1 SCL IN ts ...

  • Page 6

    ... General Purpose I/O default input. General Purpose I/O default input. General Purpose I/O default input. General Purpose I/O default input. Auto-generate Interrupt signal when detetecting a transition on GPI inputs. Reset signal input. Power Pin. Publication Release Date: Aug. 1999 - 5 - W83601R/602R Preliminary 2 C) address 2 C) address Revision 0.32 ...

  • Page 7

    ... GP Port 2: Interrupt Status Register GP Port 1: Interrupt Enable Register GP Port 2: Interrupt Enable Register Mode Configuration Register Power LED Configuration Register Reserved Register Chip ID High Byte Register Chip ID Low Byte Register (W83601R) Chip ID Low Byte Register (W83602R W83601R/602R Preliminary Publication Release Date: Aug. 1999 Revision 0.32 ...

  • Page 8

    ... W83601R/602R REGISTERS DESCRIPTIONS CR00 (GP Port 1: Input port Data Register, Default 0x-- , Read Only) This register is a data port for input only. It reflects the incoming logic levels of the pins whether the pins is defined as an input mode by CR03. It will be inverted data by CR02. Bit GP17 ~ GP10 Input Data Port. ...

  • Page 9

    ... This register will latch Port 2 data while power on or RST# pin low, which is controlled by CR14h bit 1 . Bit 7: Reserved. Bit GP26 ~ GP20 Input latched data, which bit 2-0 are SMBus address bit A2-A0 . CR0E-0F Reserved Register W83601R/602R Publication Release Date: Aug. 1999 - 8 - Preliminary ...

  • Page 10

    ... Bit Set INT output pin as pulse mode. 0, set INT output pin as level mode. Bit Set INT output pin polarity is 1 (normal high set INT output pin polarity is 0 (normal low). This bit is only for W83601R. Bit Port 2 (CR09h-CR0Ch,CR11h,CR13h) registers can be reset to default data by RST# pin. 0 ,Port 2 (CR09h-CR0Ch) can not be reset by RST# pin ...

  • Page 11

    ... CR16-1F Reserved Register CR20 (Chip ID High Byte, Read Only) Bit 7 0x60. CR21 (Chip ID Low Byte, Read Only) Bit 7 0x12 (for W83601R). = 0x22 (for W83602R). NOTE: W83602R has no GP22-GP26. All the corresponding register has no effect on W83602R. W83601R/602R Publication Release Date: Aug. 1999 ...

  • Page 12

    ... CTLSTRV TIMING WAVEFORMS (ONLY FOR W83602R) FIRST STATE ~ 5VSB S5IN# PS_ON# CTLSTRV DRAM_VOLTAG E *NOTE 1: IT CAN WAKE UP POWER FROM POWER BUTTON, KEYBOARD/MOUSE, *NOTE 2: IT CAN SUSPEND TO RAM SPECIAL DEFINED BUTTON. W83601R/602R SUSPEND RESUME POWER ON to RAM from STATE ~ ~ S3 STATE ~ ~ S0 STATE ~ POWER * NOTE1 ...

  • Page 13

    ... Suspend to RAM Resume from S3 Power state ~ ~ S3 STATE ~ t1= 5+1ms T2=500+125MS 3VSB 3VCC 3VSB Output Port Output Value at Pin Register write 1 Active write 1 Active - 12 - W83601R/602R Preliminary Soft OFF ~ S0 state ~ ~ S5 state ~ t1= 5+1ms T2=500+125MS 3VCC 3VSB Wave Publication Release Date: Aug. 1999 Revision 0.32 ...

  • Page 14

    ... Once a transition occurs at GPI input pins, interrupt status registers(CR10, CR11) will be set. At the mean time, if interrupt function is enable, INT pin will generate a interrupt. Reading these interrupt registers will clear themselves and reset interrupt interrupt occurs but no read to interrupt status registers, interrupt will not be generated again. W83601R/602R Output Wave 1 ...

  • Page 15

    PACKAGE DRAWING AND DIMENSIONS 20 SSOP-209 mil SEATING PLANE Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: ...

  • Page 16

    ... GP20/A0 4 GP21 GP21/A1 5 CTL3VSB GP22/A2/CTL3VSB 6 R2 GP10 GP10 R1 7 GP11 GP11 8 10K CTLSTRV GP23/CTLSTRV 10K 9 SLP_S5# GP24/S5IN# 10 VSS W83601R/602R SMBus Address 30 5VSB 5VSB R10 R11 1K 4. R13 PMOS IRF9531 S GP22 Q4 CTL3VSB NPN 3904 330 U1 LT1084_M 5VSB 5VSB R16 R17 ...

  • Page 17

    ... REV Decription 0.1 First Publication 0.2 Change CTL3VSB, CTLSTRV Schematic Winbond Electronic Corp. Title W83601R/602R Example Application Circuit Size Document Number Custom 602ap.sch Date: Friday, August 13, 1999 Sheet 2 Rev 0 ...