w83194br-sd

Manufacturer Part Numberw83194br-sd
DescriptionWinbond Clock Generator For Intel P4 Springdale Series Chipset
ManufacturerWinbond Electronics Corp America
w83194br-sd datasheet
 


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W83194BR-SD
W83194BG-SD
Winbond Clock Generator For
I
NTEL P4 Springdale Series Chipset
Date: Mar./22/2006
Revision: 1.2

w83194br-sd Summary of contents

  • Page 1

    ... W83194BR-SD W83194BG-SD Winbond Clock Generator For I NTEL P4 Springdale Series Chipset Date: Mar./22/2006 Revision: 1.2 ...

  • Page 2

    ... CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET W83194BR-SD/W83194BG-SD Revision history VERSION DATE 0.5 07/07/03 0.6 12/18/03 1.0 05/05/04 1.1 4/13/2005 1.2 12/20/2005 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. ...

  • Page 3

    ... Register 13: Control (Default = 0FH) ............................................................................ 12 7.15 Register 14: Control (Default = 27H) ............................................................................ 13 7.16 Register 15: Control (Default =3CH)............................................................................. 13 7.17 Register 16: Control (Default = 24H) ............................................................................ 13 7.18 Register 17: Slew Rate Control (Default = 00H)........................................................... 14 7.19 Register 18: Slew Rate Control (Default = 00H)........................................................... 14 7.20 Register 19: Control (Default = 0AH)............................................................................ 15 7.21 Register 20: Winbond Chip ID – Project Code (Ready Only) (Default = 47H) ............. 15 W83194BR-SD/W83194BG- ...

  • Page 4

    ... CPU 0.7V Electrical Characteristics ............................................................................. 19 9.5 SRC 0.7V Electrical Characteristics ............................................................................. 19 9.6 3V66 Electrical Characteristics ..................................................................................... 19 9.7 PCI Electrical Characteristics ....................................................................................... 20 9.8 24M, 48M Electrical Characteristics ............................................................................. 20 9.9 REF Electrical Characteristics ...................................................................................... 20 10. ORDERING INFORMATION..................................................................................................... 21 11. HOW TO READ THE TOP MARKING...................................................................................... 21 12. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 22 W83194BR-SD/W83194BG-SD Publication Release Date: March, 22, 2006 - III - Revision 1.2 ...

  • Page 5

    ... The W83194BR-SD also has watchdog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. The W83194BR-SD accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. 2. FEATURES • 2 pairs current mode differential clock for CPU and Chipset • ...

  • Page 6

    ... Internal Pull-down resistor 120KΩ to GND 4. BLOCK DIAGRAM < > & & & W83194BR-SD/W83194BG- REF2 XIN 5 43 ...

  • Page 7

    ... VCH_EN 3V66_0, 31, 30, 27 3V66_1, 3V66_2 PCICLK_F0 8 & FS2 W83194BR-SD/W83194BG-SD DESCRIPTION Input Latch input pin and internal 120KΩ pull down Latch input pin and internal 120KΩ pull up Output Open Drain Bi-directional Pin Bi-directional Pin, Open Drain Active Low Internal 120kΩ ...

  • Page 8

    ... OUT 5.4 I2C Control Interface PIN PIN NAME TYPE 33 SDATA* I/OD 32 SCLK* IN W83194BR-SD/W83194BG-SD TYPE OUT PCI clock output. Latched input for FS4 at initial power up for H/W selecting IN the output frequency clocks. This is internal 120KΩ pull td120k down. OUT PCI clock outputs. OUT PCI clock outputs ...

  • Page 9

    ... VDDCPU 48 VDDA 7, 12, 18, 24, GND 29, 38, 44, 47 W83194BR-SD/W83194BG-SD DESCRIPTION Deciding the reference current for the CPUCLK pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current. The table is show as follows. Board Target Trace Reference R, Iref R = 475 Iref = 50 Ohms 2 ...

  • Page 10

    ... W83194BR-SD/W83194BG-SD FS0 CPU (MHZ) SRC (MHZ) 0 100.0 100/200 1 200.0 100/200 0 133.3 100/200 1 166.6 100/200 0 200.0 100/200 1 400.0 100/200 0 266.6 100/200 1 333.3 100/200 0 100.9 100/200 1 ...

  • Page 11

    ... X 1 FS1 X 0 FS0 X W83194BR-SD/W83194BG-SD DESCRIPTION Software frequency table selection through I Enable software table selection FS [4:0 Hardware table setting (Jump mode Software table setting through Bit7~3. (Jump less mode) Enable spread spectrum mode under clock output Spread Spectrum mode disable ...

  • Page 12

    ... REF1 1 2 REF0 1 1 MODE1 0 0 MODE0 0 W83194BR-SD/W83194BG-SD DESCRIPTION Pin 10 PCI_F2 output control Pin 9 PCI_F1 output control Pin 8 PCI_F0 output control Reserved Pin 20 PCI5 output control Pin 19 PCI4 output control Reserved Pin 16 PCI3 output control DESCRIPTION Pin 15 PCI2 output control ...

  • Page 13

    ... SAF_FREQ [ SAF_FREQ [ SAF_FREQ [ SAF_FREQ [ SAF_FREQ [0] 0 W83194BR-SD/W83194BG-SD CPU OVER CLOCK MODE 00 01 Byte 8 & 9 Byte 4 & 10 (asynchronous) Byte 4 & 10 (asynchronous) CPU is effective Only. Effective DESCRIPTION Pin MHz output selection 1: 24 MHz MHz. (Default) Default value follow hardware trapping data on SEL24_48# pin. ...

  • Page 14

    ... M_DIV [ M_DIV [0] 0 W83194BR-SD/W83194BG-SD DESCRIPTION Setting the down count depth. One bit resolution represents 250 mS. Default time depth is 8*250 mS = 2.0 second. If the watchdog timer is counting, this register will return present down count value. DESCRIPTION Tri-state all output if set 1 Reserved ...

  • Page 15

    ... SP_DOWN [ SP_DOWN [ SP_DOWN [0] 1 W83194BR-SD/W83194BG-SD DESCRIPTION Programmable N divisor value bit The bit 8 is defined in Register 7. DESCRIPTION Reserved Programmable N3 divisor bit for synchronism SRC/AGP/PCI clock. DESCRIPTION Spread Spectrum Up Counter bit 3 ~ bit 0. Spread Spectrum Down Counter bit 3 ~ bit 0 2’ ...

  • Page 16

    ... IVAL<1> IVAL<0> 1 W83194BR-SD/W83194BG-SD DESCRIPTION SRC frequency select, 1: 100 MHz, 0: 200 MHz Define the AGP divider ratio, Table-2 integrate the all divider configuration Define the AGP divider ratio Table-2 integrate the all divider configuration Define the SRC divider ratio ...

  • Page 17

    ... PWD 7 INV_AGP 0 6 INV_PCI 0 W83194BR-SD/W83194BG-SD DESCRIPTION CPUT output state in during POWER DOWN or Stop mode assertion. 1: Driven (2*Iref), 0: Tristate (Floating) CPUC always tri-state (floating) in power down Assertion. SRC_T output state in during POWER DOWN or Stop mode assertion. 1: Driven (6*Iref), 0: Tristate (Floating) SRC_C always tri-state (floating) in power down Assertion. ...

  • Page 18

    ... PCI_10_S1 0 1 REF_S2 0 0 REF_S1 0 W83194BR-SD/W83194BG-SD DESCRIPTION CPU to SRC skew control CPU to PCI skew control DESCRIPTION PCI_F2 slew rate control 11: Strong, 00: Weak, 10/01: Normal PCI_F1 / PCI_F0 slew rate control 11: Strong, 00: Weak, 10/01: Normal 3V66_3 / 3V66_2 slew rate control 11: Strong, 00: Weak, 10/01: Normal ...

  • Page 19

    ... Invert the USB48 phase 0: In phase with DOT48, 1: 180 degrees out of phase USB48/DOT48/USB24_48 slew rate control 11: Strong, 00: Weak, 10/01: Normal Invert the SRC phase, 0: Default, 1: Inverse DESCRIPTION Winbond Chip ID. W83194BR-SD (SA5847). Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. ...

  • Page 20

    ... CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET 7.22 Register 21: Reserved (Ready Only) (Default = 50H) BIT NAME PWD 7 Reserved 0 6 Reserved 1 5 Reserved 0 4 Reserved 1 3 Reserved 0 2 Reserved 0 1 Reserved 0 0 Reserved 0 W83194BR-SD/W83194BG-SD DESCRIPTION Reserved Reserved Reserved Reserved - 16 - ...

  • Page 21

    ... CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET 8. ACCESS INTERFACE The W83194BR-SD provides I W83194BR-SD is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I address is defined at 0xD2. Block Read and Block Write Protocol 8.1 Block Write Protocol 8.2 Block Read Protocol ## In block mode, the command code must filled 00H 8 ...

  • Page 22

    ... Skew Group Timing Clock VDDREF = VDDA = VDDCPU = VDD3V66 = VDDPCI = VDD48 = 3.3V ± 0°C to +70° PARAMETER 3V66 to PCI Skew CPU to CPU Skew 3V66 to 3V66 Skew PCI to PCI Skew 48 MHz to 48 MHz Skew REF to REF Skew W83194BR-SD/W83194BG-SD SYM. MIN. MAX. UNITS V 0 ...

  • Page 23

    ... Test load 10pF A PARAMETER Rise Time Fall Time Cycle to Cycle Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max. W83194BR-SD/W83194BG-SD MIN. MAX. UNITS 175 700 pS 100 to 200 MHz 175 700 pS ...

  • Page 24

    ... VDDREF= 3.3V ± 0°C to +70°C, Test load PARAMETER Rise Time Fall Time Cycle to Cycle Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max. W83194BR-SD/W83194BG-SD MIN. MAX. UNITS 500 2000 pS Measure from 0.4V to 2.4V 500 2000 pS Measure from 2 ...

  • Page 25

    ... ORDERING INFORMATION PART NUMBER W83194BR-SD W83194BG-SD 11. HOW TO READ THE TOP MARKING 1st line: Winbond logo and the type number: W83194BR-SD, W83194BG-SD 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 340 340: packages made in '2003, week 40 G: assembly house ID ...

  • Page 26

    ... Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83194BR-SD/W83194BG-SD Important Notice - 22 - ...