w83194br-sd Winbond Electronics Corp America, w83194br-sd Datasheet - Page 11

• Manufacturer Part Number: w83194br-sd
• Description: Winbond Clock Generator For Intel P4 Springdale Series Chipset
• Manufacturer: Winbond Electronics Corp America

7. I
(The register No. Is increased by 1 if use byte data read/write protocol)
7.1
7.2
BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
2
Register 0: Frequency Select (Default =10H)
Register 1: SRC/CPU Clock (1 = Enable, 0 = Disable) (Default = E3H)
C CONTROL AND STATUS REGISTERS
EN_SAFE_FRE
CPUCLKC1
CPUCLKC0
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
CPUCLKT1
CPUCLKT0
SRCCLKC
EN_SSEL
SRCCLKT
SPSPEN
SSEL [4]
SSEL [3]
SSEL [2]
SSEL [1]
SSEL [0]
NAME
NAME
FS4
FS3
FS2
FS1
FS0
Q
PWD
PWD
0
0
0
1
0
0
0
0
X
X
X
X
X
1
1
1
Software frequency table selection through I
Enable software table selection FS [4:0].
0 = Hardware table setting (Jump mode).
1 = Software table setting through Bit7~3. (Jump less mode)
Enable spread spectrum mode under clock output.
0 = Spread Spectrum mode disable
1 = Spread Spectrum mode enable
After watchdog timeout
0 = Reload the hardware FS [4:0] latched pins setting.
1 = Reload the desirable frequency table selection defined at Reg-5
Bit 4~0.
Pin 37,36 SRCCLK T/C output control
Pin 43,42 CPUCLKT1/C1 output control
Pin 40,39 CPUCLKT0/C0 output control
Power on latched value of FS4 (9) pin, Default 0 (Read only)
Power on latched value of FS3 (22) pin. Default 0 (Read only)
Power on latched value of FS2 (8) pin. Default 0 (Read only)
Power on latched value of FS1 (1) pin. Default 1 (Read only)
Power on latched value of FS0 (2) pin. Default 1 (Read only)
W83194BR-SD/W83194BG-SD
- 7 -
DESCRIPTION
DESCRIPTION
Publication Release Date: March, 22, 2006
2
C
Revision 1.2