w83195bg-120 Winbond Electronics Corp America, w83195bg-120 Datasheet
w83195bg-120
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w83195bg-120 Summary of contents
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... Winbond CLOCK GENERATOR W83195BR-120/W83195BG-120 For INTEL 915/945 Chipset Date: Jan./23/2006 Revision: 0.61 ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83195BR-120/W83195BG-120 Versi Web on Version All of the versions before 0 ...
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... Register 16: Skew Control (Default: E4h) .............................................................................14 7.18 Note: The skew rate control select bit fit value Please felloe below table............................14 7.19 Register 17: Slew rate Control (Default: 00h)........................................................................15 7.20 Register 18: Reserved (Default: 00h) ....................................................................................15 7.21 Register 19: Skew Control (Default: DAh).............................................................................15 7.22 Register 20: Watch dog timer (Default: 88h).........................................................................16 W83195BR-120/W83195BG-120 -II- ...
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... SRC 0.7V Electrical Characteristics ......................................................................................19 9.6 PCIE 0.7V Electrical Characteristics......................................................................................20 9.7 PCI Electrical Characteristics.................................................................................................20 9.8 24M, 48M Electrical Characteristics ......................................................................................20 9.9 REF Electrical Characteristics ...............................................................................................21 9.10 DOT 0.7V Electrical Characteristics ......................................................................................21 10. ORDERING INFORMATION..................................................................................................... 22 11. HOW TO READ THE TOP MARKING...................................................................................... 22 12. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 23 W83195BR-120/W83195BG-120 Publication Release Date: January 2006 - III - Revision 0.61 ...
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... Programmable registers to enable/disable each output and select modes. • Programmable clock outputs slew rate control and skew control. • Watch Dog Timer and RESET# output pins. • 56 pin SSOP package. W83195BR-120/W83195BG-120 2 C serial bus interface to program the registers to enable or disable - 1 - Publication Release Date: January 2006 Revision 0 ...
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... DOTT DOTC VTT_PWRGD#/PD PCIET0 PCIEC0 VDDPE GND PCIET1 PCIEC1 PCIET2 PCIEC2 GND SRCT SRCC VDDS #: Active low *: Internal pull up resistor 120K to VDD &: Internal Pull-down resistor 120K to GND W83195BR-120/W83195BG-120 1 56 VDDP 2 55 PCI1 3 54 PCI0 4 53 RESET REF GND ...
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... & W83195BR-120/W83195BG-120 ...
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... ITP_EN PCI_F1 8 & FS0 PCI_F2 9 *FS1 54,55,2,3 PCI [0:3] W83195BR-120/W83195BG-120 DESCRIPTION Input Latched input at power up, internal 120kΩ pull up. Latched input at power up, internal 120kΩ pull down. Output Open Drain Bi-directional Pin, Open Drain. Active Low Internal 120kΩ pull-up Internal 120 kΩ pull-down ...
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... PIN PIN NAME 39 IREF 53 RESET# VTT_PWRGD W83195BR-120/W83195BG-120 TYPE OUT 3.3V REF 14.318 Mhz clock output. Latched input for FS2 at initial power up for H/W selecting IN td120k the output frequency, This pin has internal 120K pull down. 24MHz or 48MHz (default) clock output, In power on reset ...
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... VDDPE 28 VDDS 10 VDD48 43 VDDC 48 VDDR 38 GNDA 1,4,13,20,25, GND 29,40,51 W83195BR-120/W83195BG-120 TYPE DESCRIPTION PWR 3.3V power supply for PLL core. PWR 3.3V power supply for PCI. PWR 3.3V power supply PWR 3.3V power supply for PCI express pair. PWR 3.3V power supply for SRC pair. PWR 3.3V power supply for 48MHz. ...
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... W83195BR-120/W83195BG-120 CPU (MHZ) PCIE (MHZ) FS0 0 266.66 1 133.33 0 200.00 1 166.66 0 333.33 1 100.00 0 400.00 1 200.00 0 266.66 1 133.33 0 200.00 1 166.66 0 333.33 1 100.00 0 400.00 1 200.00 0 269.33 1 134 ...
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... X Power on latched value of FS1 pin, Default: 1 (Read only Power on latched value of FS0 pin, Default: 0 (Read only). W83195BR-120/W83195BG-120 DESCRIPTION Frequency selection by software via I Enable software table selection FS [4:0 Hardware table setting Software table setting through Bit 7~3. Enable spread spectrum mode at clock outputs ...
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... Register 4: 24_48MHz, 48MHz, REF Control (1 = Enable Disable) (Default: FFh) BIT PIN NO PWD 24_48MHz output control 6 14,15 1 DOT_T/C output control 48MHz output control 4 Reserved 1 Reserved 3 Reserved 1 Reserved REF output control 1 Reserved 1 Reserved 0 Reserved 1 Reserved W83195BR-120/W83195BG-120 DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: January 2006 - 9 - Revision 0.61 ...
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... PCIEEN<3> PCIEEN<2> PCIEEN<1> PCIEEN<0> Reserved 0 W83195BR-120/W83195BG-120 DESCRIPTION reading this bit returns reading this bit returns DESCRIPTION SRCCLKT/C output control Reserved PCIET4/C4 output control PCIET3/C3 output control PCIET2/C2 output control PCIET1/C1 output control PCIET0/C0 output control Reserved -10- 1 ...
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... Register 9: M/N Program Register (Default: BBh) BIT NAME PWD 7 N_DIV [ N_DIV [ N_DIV [ N_DIV [4] 1 Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register 8. 3 N_DIV [ N_DIV [ N_DIV [ N_DIV [0] 1 W83195BR-120/W83195BG-120 DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: January 2006 - 11 - Revision 0.61 ...
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... BIT5 MSB 0 Bit2/ 0 Div12 Bit4/ 1 Div20 Bit6 W83195BR-120/W83195BG-120 DESCRIPTION Enable SRCLOOP spread spectrum feature 1: Enable, 0: Disable Programmable N3 divisor bit 6 ~0 for programmable DESCRIPTION DESCRIPTION Reserved Define the PCI divider ratio Table-2 integrate the all divider configuration Define the PCIE divider ratio ...
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... SPCNT [ SPCNT [ SPCNT [0] 0 W83195BR-120/W83195BG-120 DESCRIPTION 0: using frequency table 1: using M/N register to synthesize clock frequency The equation is VCO =14.318MHz*(N+4 Once the watchdog timer times out, the bit will be cleared. Then the frequency will be decided by hardware strapping FS<2:0> or frequency select bits SAF_FREQ [4:0] when EN_SAFE_FREQ (Reg0 - bit 0) is set ...
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... Note: The skew rate control select bit fit value Please felloe below table SKEW bit[2:0] Unit Note: Each unit means 300ps Note: skew bits only for Winbond internal and BOIS program use; the release version please reserved these bits. W83195BR-120/W83195BG-120 DESCRIPTION DESCRIPTION 000 001 010 ...
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... Reserved 0 1 Reserved 1 0 Reserved 0 W83195BR-120/W83195BG-120 DESCRIPTION CPUCLK_ITP/PCIEX5 output selection, 1: CPUCLK_ITP, 0: PCIEX5 (Default). Default value follow hardware trapping data on ITP_EN/PCICLK_F0 pin. Invert the 48MHz phase phase with 24_48MHz 1: 180 degrees out of phase PCI_F0 slew rate control 11 : Strong , 00 : Weak , 10/01 : Normal ...
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... Reserved 1 Reserved SRC_BASE3 1: Asynchronous PCIE / PCI always at 100MHz / 33MHz 2 0 FIX_ADDR<1> Asynchronous PCIE / PCI frequency table selection 1 1 FIX_ADDR<1:0> => FIX_ADDR<0> W83195BR-120/W83195BG-120 DESCRIPTION DESCRIPTION 0: PCIE / PCI frequency are follow Bit1, 0 setting 00 36MHz 32MHz 10: 128 / 38.4MHz 11 : Output from PLL1 -16- TYPE R/W R/W R/W R/W R/W ...
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... In byte mode, byte number of program register is 2 (Byte number of block mode +1) 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 8’h00 8.3 Byte Write protocol 8.4 Byte Read protocol W83195BR-120/W83195BG-120 2 C Serial Bus for microprocessor to read/write internal registers. In the - Publication Release Date: January 2006 Revision 0.61 ...
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... Output pin capacitance Input pin inductance 9.3 Skew Group timing clock ± ° VDD = 3. +70 PARAMETER CPU pair to CPU pair Skew PCIE pair to PCIE pair Skew PCI to PCI Skew 48MHz to 48MHz Skew W83195BR-120/W83195BG-120 ° C, SYMBOL MIN MAX UNITS V 0 2.0 V ...
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... Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF PARAMETER Rise Time Fall Time Absolute crossing point Voltages Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle W83195BR-120/W83195BG-120 ° ° +70 C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, MIN MAX UNITS 175 700 ps Measure Single Ended waveform ...
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... +70 PARAMETER Rise Time Fall Time Long term jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max W83195BR-120/W83195BG-120 ° ° +70 C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, MIN MAX UNITS 175 700 ps Measure Single Ended waveform ...
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... Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF PARAMETER Rise Time Fall Time Absolute crossing point Voltages Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle W83195BR-120/W83195BG-120 ° C, Test load, Cl=10pF, MIN MAX UNITS 500 2000 ps Vol=0.4V, Voh=2.4V 500 2000 ps Voh=2.4V, Vol=0.4V ...
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... HOW TO READ THE TOP MARKING W83195BR-120 28051234 511GBASA 1st line: Winbond logo and the type number: Normal part:W83195BR-120 , Lead free part: W83195BG-120 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code ...
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... Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83195BR-120/W83195BG-120 SYMBOL .045 .055 A ...