w79e532 Winbond Electronics Corp America, w79e532 Datasheet
w79e532
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w79e532 Summary of contents
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... The Loader Program Locates at APFlash Memory ....................................................... 59 16. H/W WRITER MODE........................................................................................................................... 59 17. SECURITY BITS.................................................................................................................................. 60 18. ELECTRICAL CHARACTERISTICS.................................................................................................... 61 18.1 Absolute Maximum Ratings ........................................................................................... 61 18.2 DC Characteristics......................................................................................................... 61 18.3 A.C. Characteristics ....................................................................................................... 63 19. TYPICAL APPLICATION CIRCUITS ................................................................................................... 68 20. PACKAGE DIMENSIONS.................................................................................................................... 69 21. APPLICATION NOTE .......................................................................................................................... 71 22. REVISION HISTORY........................................................................................................................... 76 W79E532/W79L532 Data Sheet 8-BIT MICROCONTROLLER Publication Release Date: November 21, 2005 - 1 - Revision A5 ...
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... PWM Software Reset x x Software programmable access cycle to external RAM/peripherals x Code protection Packages DIP 40: W79E532A40DN, W79L532A25DN PLCC 44: W79E532A40PN, W79L532A25PN QFP 44: W79E532A40FN, W79L532A25FN Lead Free (RoHS)DIP 40: Lead Free (RoHS)PLCC 44: W79E532A40PL, W79L532A25PL Lead Free (RoHS)QFP 44: W79E532A40DL, W79L532A25DL W79E532A40FL, W79L532A25FL - 2 - W79E532/W79L532 ...
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... OPERATING DEVICE FREQUENCY W79E532 up to 40MHz W79L532 up to 25MHz 3. PIN CONFIGURATIONS OPERATING VOLTAGE NORMAL 4.5V ~ 5.5V DIP44, PLCC44, QFP44 3.0V ~ 5.5V DIP44, PLCC44, QFP44 Publication Release Date: November 21, 2005 - 3 - W79E532/W79L532 PACKAGE LEAD FREE(RoHS) DIP44, PLCC44, QFP44 DIP44, PLCC44, QFP44 Revision A5 ...
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... T1(P3.5) WR (P3.6) : External Data Memory Write Strobe RD (P3.7) : External Data Memory Read Strobe PORT 4: Port 4-bit bi-directional I/O port. The P4.3 also provides the I/O P4.0 P4.3 alternate function REBOOT which is H/W reboot from LD flash. * Note: TYPE I : input, O: output, I/O: bi-directional. DESCRIPTIONS : Timer 0 External Input : Timer 1 External Input - 4 - W79E532/W79L532 ...
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... Timer 1 1 UARTs Port 3 Port P3.0 Latch 3 P3.7 Port 4 Latch P4.0 Port 4 Oscillator P4.3 XTAL1 XTAL2 W79E532/W79L532 ACC B T1 Register T2 Register Stack PSW Pointer ALU SFR RAM Address Instruction Decoder & Sequencer 256 bytes RAM & SFR 1KB SRAM Bus & lock Controller Reset Block ...
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... The W79E(L)532 has one enhanced serial ports that are functionally similar to the serial port of the original 8052 family. However the serial ports on the W79E(L)532 can operate in different modes in order to obtain timing similarity as well. The serial port has the enhanced features of Automatic Address recognition and Frame Error detection. W79E532/W79L532 - 6 - ...
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... MOVX SRAM is enabled by setting the DME0 bit in the PMR register. After a reset, the DME0 bit is cleared such that the on-chip MOVX SRAM is disabled, and all data memory spaces 0000H FFFFH access to the external memory. W79E532/W79L532 Publication Release Date: November 21, 2005 - 7 - Revision A5 ...
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... FFh Indirect SFRs Addressing Direct RAM Addressing 80h 7Fh Direct & Indirect Addressing RAM 00h 03FFh 1K Bytes On-chip SRAM 0000h W79E532/W79L532 FFFFh 64K Bytes 64K Bytes On-chip 64 K Program Bytes Memory External Data Memory APFlash0 0000h Figure 1. Memory Map - 8 - On-chip Program ...
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... XRAMAH P4CSIN 98 SCON0 SBUF P42AL 90 P1 P4CONA 88 TCON TMOD TL0 DPL Note: The SFRs in the column with dark borders are bit-addressable. W79E532/W79L532 PWM1 PWMCON1 PWM2 RCAP2H TL2 TH2 PWM5 PMR STATUS ROMCON SFRAL SFRAH P4 P42AH P43AL P43AH P4CONB P40AL P40AH ...
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... GF1-0: These two bits are general purpose user flags P0.6 P0.5 P0.4 P0 SP.6 SP.5 SP.4 SP DPL.6 DPL.5 DPL.4 DPL DPH.6 DPH.5 DPH.4 DPH GF1 SMOD0 - 10 - W79E532/W79L532 P0.2 P0.1 P0.0 Address: 80h SP.2 SP.1 SP.0 Address: 81h DPL.2 DPL.1 DPL.0 Address: 82h DPH.2 DPH.1 DPH.0 Address: 83h ...
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... Timer Mode Control Bit: 7 GATE Mnemonic: TMOD GATE: Gating control: When this bit is set, Timer/counter x is enabled only while INTx pin is high and TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set. W79E532/W79L532 TR1 TF0 ...
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... TL0.70: Timer 0 LSB Timer 1 LSB Bit: 7 TL1.7 Mnemonic: TL1 TL1.70: Timer 1 LSB Timer 0 MSB Bit: 7 TH0.7 Mnemonic: TH0 TH0.70: Timer 0 MSB Timer 1 MSB Bit: 7 TH1.7 Mnemonic: TH1 TH1.70: Timer 1 MSB W79E532/W79L532 MODE TL0.6 TL0.5 TL0.4 TL0 TL1.6 TL1.5 TL1.4 TL1 TH0 ...
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... Publication Release Date: November 21, 2005 - 13 - W79E532/W79L532 T0M MD2 MD1 Address: 8Eh Reset time-out 512 512 512 512 ...
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... Compare the 8 high bits (A15-A8) of address bus with the base address registers P4xAH and P4xAL P1.6 P1.5 P1.4 P1 P41M0 P41C1 P41C0 P40M1 P43M0 P43C1 P43C0 P42M1 FUNCTION - 14 - W79E532/W79L532 P1.2 P1.1 P1.0 Address: 90h P40M0 P40C1 P40C0 Address: 92h P42M0 P42C1 P42C0 Address: 93h ...
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... A14 A13 A12 SM1 SM2 REN Description Length 0 Synchronous 8 1 Asynchronous 10 2 Asynchronous 11 3 Asynchronous 11 Publication Release Date: November 21, 2005 - 15 - W79E532/W79L532 Address: 94h A11 A10 A9 A8 Address: 95h Address: 96h ...
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... A7 Mnemonic: P42AL P4.2 Base Address High Byte Register Bit: 7 A15 Mnemonic: P42AH P4.3 Base Address Low Byte Register Bit Mnemonic: P43AL P4.3 Base Address High Byte Register Bit: 7 A15 Mnemonic: P43AH W79E532/W79L532 A14 A13 ...
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... P2.7-0: Port bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. Port 4 Chip-select Polarity Bit: 7 P43INV P42INV P42INV P40INV Mnemonic: P4CSIN P4xINV: The active polarity of P4.x when set it as chip-select signal. High = Active High. Low = Active Low. P0UP: Enable Port 0 weak pull up. W79E532/W79L532 LDAP - - 6 ...
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... DCP11 0 DCP10 ES1 ET2 P1.1 P1.2 P1 W79E532/W79L532 P4.3 P4.2 P4.1 Address: A5h ET1 EX1 ET0 Address: A8h Address: A9h EN128K DCP12 DCP11 DCP10 Address: ABh P1.4 P1.5 P1 P4.0 0 EX0 ...
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... WFWIN NOE NCE CTRL3 WFWIN NOE NCE CTRL<3:0> 0010 0010 0010 0001 Publication Release Date: November 21, 2005 - 19 - W79E532/W79L532 Address: ACh A10 A9 A8 Address: ADh Address: AEh 3 ...
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... Strobe for write to external RAM Timer/counter 1 external count input Timer/counter 0 external count input External interrupt 1 External interrupt 0 Serial port 0 output Serial port 0 input PT2 W79E532/W79L532 SFRAH, CTRL<3:0> SFRFD SFRAL 0001 Address in Data in 0001 Address in Data in 0000 Address in Data out ...
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... Now a window is opened in the protected bits for three machine cycles, during which the user can write to these bits HIP LIP - TA.6 TA.5 TA.4 Publication Release Date: November 21, 2005 - 21 - W79E532/W79L532 Address: B9h DME0 ALE-OFF Address: C4h Address: C5h TA.3 TA.2 TA ...
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... DCEN: Down Count Enable: This bit, in conjunction with the T2EX pin, controls the direction that timer 2 counts in 16-bit auto-reload mode EXF2 RCLK TCLK EXEN2 / 2 , EXEN2 and DCEN bits. If set by a negative W79E532/W79L532 TR2 Address: C8h T2CR - - DCEN Address: C9h 0 ...
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... RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L TL2.6 TL2.5 TL2 TH2.6 TH2.5 TH2 RS1 Publication Release Date: November 21, 2005 - 23 - W79E532/W79L532 RCAP2L.0 Address: CAh Address: CBh TL2.3 TL2.2 TL2.1 TL2.0 Address: CCh TH2.3 TH2.2 TH2.1 TH2 ...
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... WDCON REG D8H CKCON REG 8EH MOV TA, #AAH MOV TA, #55H SETB WDCON.0 ORL CKCON, #11000000B MOV TA, #AAH Register bank Address 0 00-07h 1 08-0Fh 2 10-17h 3 18-1Fh POR - - ; Reset watchdog timer ; Select 26 bits watchdog timer - 24 - W79E532/W79L532 WDIF WTRF EWT RWT Address: D8h 0 ...
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... EWDI: Enable Watchdog timer interrupt B Register Bit: 7 B.7 Mnemonic: B B.7-0: The B register is the standard 8052 register that serves as a second accumulator. Extended Interrupt Priority Bit Mnemonic: EIP EIP.7-5: Reserved bits. PWDI: Watchdog timer interrupt priority. W79E532/W79L532 ; Enable watchdog ACC.6 ACC.5 ACC.4 ACC ...
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... However, in the W79E(L)532 each machine cycle is made of only 4 clock periods compared to the 12 clock periods for the standard 8032. Therefore, even though the number of categories has increased, each instruction is at least 1 times faster than the standard 8032 in terms of clock periods. W79E532/W79L532 - 26 - ...
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... PSEN AD7-0 PORT 2 Figure 3. Single Cycle Instruction Timing Instruction Fetch CLK ALE PSEN PC OP-CODE AD7-0 Address A15-8 PORT 2 Figure 4. Two Cycle Instruction Timing W79E532/W79L532 Single Cycle A7-0 Data_ in D7-0 Address A15-8 Operand Fetch PC+1 OPERAND Address A15-8 Publication Release Date: November 21, 2005 ...
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... Address A15-8 Figure 6. Four Cycle Instruction Timing Operand Fetch A7-0 OPERAND Address A15-8 Operand Fetch Operand Fetch A7-0 A7-0 OPERAND OPERAND Address A15-8 Address A15 W79E532/W79L532 Operand Fetch A7-0 OPERAND Address A15-8 Operand Fetch A7-0 OPERAND Address A15-8 ...
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... OPERAND Address A15-8 Address A15-8 Figure 7. Five Cycle Instruction Timing MACHINE STROBE WIDTH CYCLES IN CLOCKS (default Publication Release Date: November 21, 2005 - 29 - W79E532/W79L532 Operand Fetch Operand Fetch A7-0 OPERAND A7-0 OPERAND Address A15-8 Address A15 ...
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... A0-A7 D0-D7 D0-D7 Next Inst. MOVX Data Address Address . MOVX Inst Next Inst. Read A15-A8 A15-A8 Figure 8. Data Memory Write with Stretch Value = W79E532/W79L532 STROBE STROBE WIDTH WIDTH @ 25 MHZ @ 40 MHZ 480 nS 300 nS 640 nS 400 nS 800 nS 500 nS 960 nS 600 nS 1120 nS ...
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... PSEN WR D0-D7 A0-A7 A0-A7 PORT 0 MOVX Inst. Next Inst. Address Address Next Inst. MOVX Inst. PORT 2 A15-A8 A15-A8 Figure 10. Data Memory Write with Stretch Value = 2 W79E532/W79L532 First Second Third Next Instruction Machine Cycle Machine Cycle Machine Cycle MOVX instruction cycle ...
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... Then device executes the interrupt service routine for the corresponding external interrupt. After the interrupt service routine is completed, the program execution returns to the instruction after the one which put the device into Power Down mode and continues from there. W79E532/W79L532 - 32 - ...
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... ALE PORT0 PSEN 1 1 Data 1 1 Float 0 0 Data 0 0 Float Publication Release Date: November 21, 2005 - 33 - W79E532/W79L532 PORT1 PORT2 PORT3 Data Data Data Data Address Data Data Data Data Data Data Data Revision A5 ...
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... WDCON 00000001b 11111111b 00000000b P4CONB 00000000b P40AH 00000000b P41AH 00000000b P42AH 00000000b P43AH 00000000b P4CSIN 00000111b SFRAL 00000000b SFRFD - 34 - W79E532/W79L532 RESET VALUE IE 00000000b 00000000b P3 11111111b IP x0000000b 00000000b 00000000b 00000x00b 00000000b 00000000b TL2 00000000b TH2 00000000b TA 11111111b PSW 00000000b 0x0x0xx0b ...
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... RESET VALUE SFR NAME 00111111b 00000000b xxxxxxxx b 11111111b PWMCON1 00000000b PWM0 00000000b PWM2 00000000b PWM4 00000000b Watchdog reset 0x0x01x0b Publication Release Date: November 21, 2005 - 35 - W79E532/W79L532 RESET VALUE P4 xxxx 1111b B 00000000b EIP xxx00000b 00000000b 00000000b 00000000b 00000000b Power on reset 01000000b Revision A5 ...
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... This hierarchy is defined as shown below; the interrupts are numbered starting from the highest priority to the lowest. Table 7. Priority structure of interrupts SOURCE External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Port Timer 2 Overflow Watchdog Timer W79E532/W79L532 FLAG VECTOR ADDRESS IE0 0003h TF0 000Bh IE1 0013h TF1 001Bh ...
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... THx register is incremented. When the count in THx moves from FFh to 00h, then the overflow flag TFx in TCON SFR is set. The counted input is enabled only if TRx is set and either GATE = 0 or INTx = 1. When C T W79E532/W79L532 / " bit in the TMOD Special Function ...
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... TRx bit and proper setting of GATE and INTx pins the other two modes 0 and 1 mode 2 allows counting of either clock cycles (clock/12 or clock/4) or pulses on pin Tn. Timer 1 functions are shown in brackets C/T = TMOD.2 (M1,M0 = TMOD.5,TMOD.4) (C/T = TMOD. TL0 (TL1) Figure 11. Timer/Counter Mode 0 & Mode W79E532/W79L532 M1,M0 = TMOD.1,TMOD TH0 (TH1) Interrupt TFx TF0 (TF1) ...
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... Mode 3. It can also be used as a baud rate generator for the serial port. Timer 1 functions are shown in brackets C/T = TMOD.2 TL0 (C/T = TMOD.6) (TL1 TH0 (TH1) Figure 12. Timer/Counter Mode 2. Publication Release Date: November 21, 2005 - 39 - W79E532/W79L532 Interrupt 7 TFx TF0 (TF1) 7 Revision A5 ...
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... Setting the T2CR bit (T2MOD.3), the W79E(L)532 allows hardware to reset timer 2 automatically after the value of TL2 and TH2 have been captured. C/T = TMOD.2 TL0 TH0 0 Figure 13. Timer/Counter 0 Mode bit in the T2CON register the capture - 40 - W79E532/W79L532 Interrupt 7 TF0 Interrupt 7 TF1 ...
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... EXEN2 = T2CON.3 1 C/T2 = T2CON TL2 1 RCAP2L Figure 14. 16-Bit Capture Mode C/T2 = T2CON.1 0 TL2 1 RCAP2L Figure 15. 16-Bit Auto-reload Mode, Counting Up Publication Release Date: November 21, 2005 - 41 - W79E532/W79L532 T2CON.7 TH2 TF2 Timer 2 Interrupt RCAP2H EXF2 T2CON bit in the T2CON register T2CON.7 TH2 TF2 Timer 2 Interrupt RCAP2H EXF2 T2CON ...
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... T2EX pin will set EXF2 bit in the T2CON register and cause an interrupt request. /Down Down Counting Reload Value 0FFh 0FFh C/T = T2CON TL2 TH2 1 RCAP2L RCAP2H Up Counting Reload Value DCEN = 1 Figure 16. 16-Bit Auto-reload Up/Down Counter Figure 17. Baud Rate Generator Mode - 42 - W79E532/W79L532 / 2 bit in T2CON is .7 T2CON Timer 2 TF2 Interrupt EXF2 T2CON.6 ...
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... It does not have to wait until the end of the current counter period. There is weakly pulled high on PWM output. The repetition frequency u ) 255 ( PWMn) PWMn 255 - (PWMn) Publication Release Date: November 21, 2005 - 43 - W79E532/W79L532 the pwm f = 16M Hz). By loading the PWM osc Revision A5 ...
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... PWM3 Register Bit: 7 Mnemonic: PWM3 FIGURE 1 PWM DIAGRAM ; enable pwm3 enable pwm4 ; Fpwm = XT/(2*(1+pwmp)*255) ; duty cycle high/low = pwm0/(255-pmw0) ; output enable pwm3 W79E532/W79L532 Address: DEH ...
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... ENPWM3 ENPWM2 PWM1OE Publication Release Date: November 21, 2005 - 45 - W79E532/W79L532 Address: DDH PWM0OE ENPWM1 ENWPM0 Address: DCH Address: DBH Address: DAH Address: D9H Address: CFH ...
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... Reset Watchdog 23 25 RWT (WDCON. PWM5 - - OE WD1,WD0 EWDI(EIE. Time-out 11 Enable Watchdog timer reset EWT(WDCON.1) Figure 19. Watchdog Timer - 46 - W79E532/W79L532 PWM4 ENWP ENWP Address: CEH Address: C3H Interrupt WDIF WTRF 512 clock Reset delay ...
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... The control bits that support the Watchdog timer are discussed below. NUMBER OF TIME CLOCKS @ 1.8432 MHZ 131072 71.11 mS 1048576 568.89 mS 8388608 4551.11 mS 67108864 36408.88 mS Publication Release Date: November 21, 2005 - 47 - W79E532/W79L532 TIME TIME @ 10 MHZ @ 25 MHZ 13.11 mS 5.24 mS 104.86 mS 41.94 mS 838.86 mS 335.54 mS 6710.89 mS 2684.35 mS Revision A5 ...
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... Please refer as below demo program. org 63h mov TA,#AAH mov TA,#55H clr WDIF jnb execute_reset_flag,bypass_reset jmp $ bypass_reset: mov TA,#AAH mov TA,#55H setb RWT reti org 300h 17 clocks, which is the shortest time-out period. The EWT, WDIF ; Test if CPU need to reset. ; Wait to reset - 48 - W79E532/W79L532 ...
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... TA,#aah mov TA,#55h mov WDCON,#00000011B setb EWDI setb ea jmp $ ; select timer ; select timer ; select timer ; select timer ; wait time out Publication Release Date: November 21, 2005 - 49 - W79E532/W79L532 Revision A5 ...
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... Transmit Shift Register TX CLOCK TI SERIAL RI CONTROLLE SHIFT RX CLOCK CLOCK LOAD SBUF RX START RX SHIFT CLOCK PAROUT SIN Receive Shift Register Figure 20. Serial Port Mode W79E532/W79L532 RXD P3.0 Alternate Output Function Serial Port Interrupt TXD P3.1 Alternate Output function Read SBUF SBUF Internal SBUF Data Bus ...
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... If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set. Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the RxD pin. W79E532/W79L532 Publication Release Date: November 21, 2005 - 51 - ...
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... TX START TX SHIFT TX CLOCK TI SERIAL RI CONTROLLER RX CLOCK LOAD RX SBUF START RX SHIFT CLOCK PAROUT BIT SIN DETECTOR Receive Shift Register Figure 21. Serial Port Mode W79E532/W79L532 STOP PARIN SOUT TXD START LOAD CLOCK Serial Port Interrupt Read SBUF Internal SBUF D8 RB8 Data Bus ...
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... SHIFT TX CLOCK TI SERIAL CONTROLLER RI RX CLOCK LOAD RX START SBUF RX SHIFT CLOCK PAROUT BIT SIN D8 DETECTOR Receive Shift Register Figure 22. Serial Port Mode 2 Publication Release Date: November 21, 2005 - 53 - W79E532/W79L532 TXD SOUT Serial Port Interrupt Read SBUF Internal SBUF Data Bus RB8 Revision A5 ...
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... Figure 23. Serial Port Mode 3 FRAME BAUD CLOCK SIZE bits CLKS Timer bits bits T CLKS Timer bits - 54 - W79E532/W79L532 SOUT TXD Serial Port Interrupt Read SBUF Internal SBUF Data Bus D8 RB8 STAR STOP 9TH BIT ...
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... ORing of the SADDR and SADEN SFRs. The zeros in the result are defined as don't cares In most cases the Broadcast Address is FFh. In the previous case, the Broadcast Address is (1111111X) for slave 1 and (11111111) for slave 2. W79E532/W79L532 Publication Release Date: November 21, 2005 - 55 - ...
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... Example 1: Valid access MOV TA, #0AAh MOV TA, #055h MOV WDCON, #00h 3 M/C Example 2: Valid access MOV TA, #0AAh MOV TA, #055h NOP SETB EWT Example 3: Valid access MOV TA, #0Aah MOV TA, #055h ORL WDCON, #00000010B 3M/C ;define new register TA, located at 0C7h 3 M/C Note: M/C = Machine Cycles 3 M/C 3 M/C 3 M/C 1 M/C 2 M/C 3 M W79E532/W79L532 ...
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... In Example 5, the second write to TA occurs 4 machine cycles after the first write, therefore the timed access window in not opened at all, and the write to the protected bit fails. 3 M/C 3 M/C 1 M/C 1 M/C 2 M/C 3 M/C 1 M/C 3 M/C 2 M/C Publication Release Date: November 21, 2005 - 57 - W79E532/W79L532 Revision A5 ...
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... In application system design, user must take care the P4.3, P2, P3, ALE, /EA and /PSEN pin value at reset to avoid W79E(L)532 entering the programming mode or REBOOT mode in normal operation. RST P4.3 P2 The Reset Timing For Entering REBOOT Mode W79E532/W79L532 P2.6 MODE L REBOOT X REBOOT Hi-Z Hi-Z ...
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... H/W WRITER MODE This mode is for the writer to write / read Flash EPROM operation. A general user may not enter this mode. The Timing For Entering Flash EPROM EA PSEN ALE P2.7 P2.6 P3.7 P3.6 RST Mode on the Programmer 10ms 300ms Publication Release Date: November 21, 2005 - 59 - W79E532/W79L532 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Revision A5 ...
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... If this bit is set to logic 0, enable to reboot 4k LDFlash mode while RST =H and P4 state. CPU will start from LDFlash to update the user’s program B7: Select clock freqency. If clock freqency is over 24M hz, then set this bit clock frequency is less than 24M hz, then clear this bit. Security Bits Option Bits - 60 - W79E532/W79L532 ...
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... I TL -250 - 0 IL1 IL2 IL3 0 0.5 V Publication Release Date: November 21, 2005 - 61 - W79E532/W79L532 RATING UNIT +7 +0 +70 qC +150 qC TEST CONDITIONS Fosc < MHz V = 5.5V, Fosc = 20 MHz 3.3V, Fosc = 12 MHz 5.5V, Fosc=20 MHz 3.3V, Fosc=12 MHz 3 ...
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... IH3 2 Isk1 3 Isk2 6.5 9.5 -200 -360 Isr1 -100 -220 -10 -14 Isr2 - 0.45 V OL1 - 0.4 - 0.45 V OL2 - 0.4 2 OH1 1 OH2 1 W79E532/W79L532 TEST CONDITIONS UNIT 4.5V 0. 3. 0.45V 3.3V, V =0.4 DD ...
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... A.C. Characteristics Dmpdl Note: Duty cycle is 50%. External Clock Characteristics PARAMETER SYMBOL Clock High Time t CHCX Clock Low Time t CLCX Clock Rise Time t CLCH Clock Fall Time t CHCL W79E532/W79L532 t CLCL t CLCH t CLCX t t CHCL CHCX MIN. TYP. MAX Publication Release Date: November 21, 2005 ...
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... PSEN Low to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN Port 0 Address to Valid Instr. In Port 2 Address to Valid Instr. In PSEN Low to Address Float Data Hold After Read Data Float After Read RD Low to Address Float W79E532/W79L532 VARIABLE SYMBOL CLOCK MIN. 1/t 0 CLCL t 1 ...
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... CLCL t AVWL2 2. CLCL -5 t QVWX 1. CLCL CLCL t WHQX 2. CLCL t 0.5t RLAZ WHLH 1. 1.0t CLCL Publication Release Date: November 21, 2005 - 65 - W79E532/W79L532 VARIABLE CLOCK UNITS STRECH MAX MCS nS t >0 MCS MCS nS t >0 MCS MCS nS t >0 MCS - CLCL MCS nS ...
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... Logic level low P PSEN R RD signal W WR signal Z Tri-state t LLIV t PLPH t PLIV t LLPL t PLAZ t PXIX t LLAX1 INSTRUCTION A0- AVIV1 t AVIV2 ADDRESS A8-A15 - 66 - W79E532/W79L532 T MCS CLCL 8 t CLCL 12 t CLCL 16 t CLCL 20 t CLCL 24 t CLCL 28 t CLCL t PXIZ ADDRESS A0-A7 ADDRESS A8-A15 ...
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... LLDV t LLWL t RLRH t LLAX1 t RLDV t AVLL t RLAZ t AVWL1 ADDRESS DATA A0- AVDV1 t AVDV2 ADDRESS A8-A15 t LLWL t WLWH t LLAX2 t AVLL t AVWL1 t QVWX ADDRESS DATA OUT A0-A7 t AVDV2 ADDRESS A8-A15 Publication Release Date: November 21, 2005 - 67 - W79E532/W79L532 t WHLH t RHDZ t RHDX ADDRESS A0-A7 t WHLH t WHQX ADDRESS A0-A7 Revision A5 ...
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... AD4 P0.4 14 AD5 AD5 P0.5 17 AD6 AD6 P0.6 18 AD7 AD7 P0.7 1 AD8 P2.0 11 AD9 P2.1 AD10 P2.2 AD11 P2.3 AD12 P2.4 AD13 P2.5 AD14 P2.6 P2 PSEN ALE/P TXD RXD Figure W79E532/W79L532 ...
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... E Base Plane A 1 Seating Plane Publication Release Date: November 21, 2005 - 69 - W79E532/W79L532 Dimension in inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A 0.210 5.334 A 0.010 0.254 1 A 0.150 0.155 0.160 3.81 3.937 4.064 ...
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... QFP See Detail F y Seating Plane Detail W79E532/W79L532 Dimension in inch Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A --- --- --- --- --- --- A 0.002 0.01 0.02 0.25 0.05 0 0.081 0.087 1.90 2.05 2.20 0.075 2 b 0.01 0.014 0.25 0.45 0.018 ...
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... MOV TH0,R7 RETI ;************************************************************************ ;* 64K APFlash MAIN PROGRAM ;************************************************************************ ORG 100H MAIN_64K: MOV A,P1 ANL A,#01H CJNE A,#01H,PROGRAM_64K JMP NORMAL_MODE 9FH C7H ACH ADH AEH AFH ; JUMP TO MAIN PROGRAM ; TR0 = 0, STOP TIMER0 ; SCAN P1 P1 ENTER IN-SYSTEM PROGRAMMING MODE Publication Release Date: November 21, 2005 - 71 - W79E532/W79L532 Revision A5 ...
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... EQU 9FH TA EQU C7H SFRAL EQU ACH SFRAH EQU ADH SFRFD EQU AEH SFRCN EQU AFH ORG 000H LJMP 100H ; JUMP TO MAIN PROGRAM ;************************************************************************ ;* 1. TIMER0 SERVICE VECTOR ORG = 0BH ;************************************************************************ ORG 000BH CLR TR0 ; TR0 = 0, STOP TIMER0 MOV TL0, R6 MOV TH0, R7 RETI W79E532/W79L532 - 72 - ...
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... SET TIMER FOR READ OPERATION, ABOUT 1 MOV R7,#FFH MOV TL0,R6 MOV TH0,R7 BLANK_CHECK_LOOP: SETB TR0 ; ENABLE TIMER 0 MOV PCON,#01H ; ENTER IDLE MODE MOV A,SFRFD ; READ ONE BYTE CJNE A,#FFH,BLANK_CHECK_ERROR INC SFRAL ; NEXT ADDRESS DEPENDING ON USER'S SYSTEM CLOCK RATE. Publication Release Date: November 21, 2005 - 73 - W79E532/W79L532 Revision A5 ...
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... MOV DPTR,#0H ; The start address of sample code MOV R2,#0H ; Target low byte address MOV R1,#0H ; Target high byte address MOV SFRAH,R1 ; SFRAH, Target high address MOV SFRCN,#00H ; SFRCN = 00H, Read APFlash0 ; SFRCN = 80H , Read APFlash1 READ_VERIFY_64K: W79E532/W79L532 ; THIS PROGRAM IS BASED ON USER’S CIRCUIT ...
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... MOV TA,#AAH MOV TA,#55H MOV CHPCON,#83H ERROR_64K: DJNZ R4,UPDATE_64K ; IF ERROR OCCURS, REPEAT 3 TIMES SFRAL = LOW ADDRESS ; TCON = 10H, TR0 = 1,GO ; SOFTWARE RESET. CPU will restart from APFlash0 ; IN-SYST PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT. Publication Release Date: November 21, 2005 - 75 - W79E532/W79L532 Revision A5 ...
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... Add Lead Free package. - Add wide voltage device (W79L532) 3 Add device list. 42 Revise the diagram of timer2 baud rate generator mode. 44 Revise the diagram of PWM 53 Revise the diagram of serial port mode 2. 56 Modify the explanation to the TA protection example. 61 Modify DC characteristic. 68 Modify application circuit - 76 - W79E532/W79L532 DESCRIPTION ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W79E532/W79L532 Important Notice Publication Release Date: November 21, 2005 - 77 - ...