PIC12F635-I/MD Microchip Technology, PIC12F635-I/MD Datasheet - Page 111

• Manufacturer Part Number: PIC12F635-I/MD
• Description: IC PIC MCU FLASH 1KX14 8DFN
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F635-I/MD

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DFN
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164326 - MODULA SKT PM3 20QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNAC162057 - MPLAB ICD 2 HEADER 14DIPXLT08DFN - SOCKET TRANSITION ICE 8DFN
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

11.22 Low-Current Sleep Mode
The Sleep command from the microcontroller, via an
SPI Interface command, places the AFE into an ultra
Low-current mode. All circuits including the RF Limiter,
except the minimum circuitry required to retain register
memory and SPI capability, will be powered down to
minimize the AFE current draw. Power-on Reset or any
SPI command, other than Sleep command, is required
to wake the AFE from Sleep.
11.23 Low-Current Standby Mode
The AFE is in Standby mode when no LF signal is
present on the antenna inputs but the AFE is powered
and ready to receive any incoming signals.
11.24 Low-Current Operating Mode
The AFE is in Low-current Operating mode when a LF
signal is present on an LF antenna input and internal
circuitry is switching with the received data.
TABLE 11-4:
© 2007 Microchip Technology Inc.
Configuration Register 0
Configuration Register 1
Configuration Register 2
Configuration Register 3
Configuration Register 4
Configuration Register 5
Configuration Register 6
(Column Parity Register)
Register Name
AFE CONFIGURATION REGISTER PARITY BIT EXAMPLE
Bit 8
1
0
0
0
0
1
1
Bit 7
0
0
0
0
0
0
1
PIC12F635/PIC16F636/639
Bit 6
1
0
0
0
0
0
0
Bit 5
0
0
0
0
0
0
1
11.25 Error Detection of AFE
The AFE’s Configuration registers are volatile memory.
Therefore, the contents of the registers can be
corrupted or cleared by any electrical incidence such
as battery disconnect. To ensure the data integrity, the
AFE has an error detection mechanism using row and
column parity bits of the Configuration register memory
map. The bit 0 of each register is a row parity bit which
is calculated over the eight Configuration bits (from bit
1 to bit 8). The Column Parity Register (Configuration
Register 6) holds column parity bits; each bit is
calculated over the respective columns (Configuration
registers 0 to 5) of the Configuration bits. The STATUS
register is not included for the column parity bit
calculation. Parity is to be odd. The parity bit set or
cleared makes an odd number of set bits. The user
needs to calculate the row and column parity bits using
the contents of the registers and program them. During
operation, the AFE continuously calculates the row and
column parity bits of the configuration memory map. If
a parity error occurs, the AFE lowers the SCLK/ALERT
pin (interrupting the microcontroller section) indicating
the configuration memory has been corrupted or
unloaded and needs to be reprogrammed.
At an initial condition after a Power-On-Reset, the
values of the registers are all clear (default condition).
Therefore, the AFE will issue the parity bit error by
lowering the SCLK/ALERT pin. If user reprograms the
registers with correct parity bits, the SCLK/ALERT pin
will be toggled to logic high level immediately.
The parity bit errors do not change or affect the AFE’s
functional operation.
Table 11-4 shows an example of the register values
and corresponding parity bits.
Bit 4
1
0
0
0
0
0
0
Configuration Register Data
Bit 3
0
0
0
0
0
0
1
Bit 2
0
0
0
0
0
0
1
Bit 1
0
0
0
0
0
0
1
DS41232D-page 109
(Row Parity)
Bit 0
0
1
1
1
1
0
1