PIC18F23K20-I/MV Microchip Technology, PIC18F23K20-I/MV Datasheet - Page 197
![IC MCU 8BIT 8KB FLASH 28UQFN](/photos/12/13/121305/c04-152_mv_sml.jpg)
PIC18F23K20-I/MV
Manufacturer Part Number
PIC18F23K20-I/MV
Description
IC MCU 8BIT 8KB FLASH 28UQFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F23K20-I/MV
Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
28-UFQFN Exposed Pad
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
16 bit
Data Ram Size
768 B
Interface Type
MSSP, I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
A/d Bit Size
10 bit
A/d Channels Available
10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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17.3.3
To enable the serial port, SSP Enable bit, SSPEN of
the SSPCON1 register, must be set. To reset or recon-
figure SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI is automatically controlled by the SPI module
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
• SCK (Slave mode) must have corresponding
• SS must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 17-2:
2010 Microchip Technology Inc.
TRIS bit cleared
TRIS bit set
ENABLING SPI I/O
SPI Master SSPM<3:0> = 00xxb
MSb
Serial Input Buffer
Processor 1
SPI MASTER/SLAVE CONNECTION
Shift Register
(SSPBUF)
(SSPSR)
LSb
SDO
SCK
SDI
Serial Clock
17.3.4
Figure 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data–Slave sends dummy data
• Master sends data–Slave sends data
• Master sends dummy data–Slave sends data
PIC18F2XK20/4XK20
SDO
SCK
SDI
TYPICAL CONNECTION
SPI Slave SSPM<3:0> = 010xb
MSb
Serial Input Buffer
Shift Register
(SSPBUF)
(SSPSR)
Processor 2
LSb
DS41303G-page 197
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