PIC18F23K20-I/MV Microchip Technology, PIC18F23K20-I/MV Datasheet - Page 356
![IC MCU 8BIT 8KB FLASH 28UQFN](/photos/12/13/121305/c04-152_mv_sml.jpg)
PIC18F23K20-I/MV
Manufacturer Part Number
PIC18F23K20-I/MV
Description
IC MCU 8BIT 8KB FLASH 28UQFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F23K20-I/MV
Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
28-UFQFN Exposed Pad
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
16 bit
Data Ram Size
768 B
Interface Type
MSSP, I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
A/d Bit Size
10 bit
A/d Channels Available
10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PIC18F2XK20/4XK20
XORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS41303G-page 356
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
W
REG
W
Q1
=
=
=
=
register ‘f’
Exclusive OR W with f
XORWF
0 f 255
d [0,1]
a [0,1]
(W) .XOR. (f) dest
N, Z
Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
XORWF
Read
0001
Q2
AFh
B5h
1Ah
B5h
REG, 1, 0
f {,d {,a}}
10da
Process
Data
Q3
ffff
destination
Write to
Q4
ffff
2010 Microchip Technology Inc.
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