AT89LP4052-20XU Atmel, AT89LP4052-20XU Datasheet - Page 76

IC 8051 MCU FLASH 4K 20TSSOP

AT89LP4052-20XU

Manufacturer Part Number
AT89LP4052-20XU
Description
IC 8051 MCU FLASH 4K 20TSSOP
Manufacturer
Atmel
Series
89LPr
Datasheet

Specifications of AT89LP4052-20XU

Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
UART, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
15
Number Of Timers
2
Operating Supply Voltage
2.4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89ISP
Minimum Operating Temperature
- 40 C
Package
20TSSOP
Device Core
8051
Family Name
AT89
Maximum Speed
20 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
23.5.4
23.5.5
76
AT89LP2052/LP4052
ISP Exit Sequence
ISP Byte Sequence
Execute this sequence to exit ISP and resume execution.
Figure 23-25. In-System Programming (ISP) Exit Sequence
Note:
The ISP byte sequence is shown in
Figure 23-26. ISP Byte Sequence
1. Bring SS (P1.4) to “H”.
2. Tri-state MOSI (P1.5).
3. Tri-state SCK (P1.7).
4. Bring RST to “L”.
5. Tri-state SS.
• Data shifts in/out MSB first.
• MISO changes at falling edge of SCK.
• MOSI is sampled at rising edge of SCK.
The waveforms on this page are not to scale.
MOSI
MISO
SCK
XTAL1
MISO
MOSI
RST
SCK
V
SS
CC
7
7
6
6
Data Sampled
Figure
5
5
23-26.
4
4
HIGH Z
HIGH Z
3
3
2
2
1
1
3547J–MICRO–10/09
0
0

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