PIC16F1938-I/ML Microchip Technology, PIC16F1938-I/ML Datasheet - Page 336

• Manufacturer Part Number: PIC16F1938-I/ML
• Description: IC MCU 8BIT FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1938-I/ML

• Core Size: 8-Bit
• Program Memory Size: 28KB (16K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1024Byte
• Cpu Speed: 32MHz
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/USART
• On-chip Adc: 11-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F193X/LF193X
24.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
• If the interrupt occurs during or after the
FIGURE 24-1:
TABLE 24-1:
DS41364C-page 336
Name
IOCBF
IOCBN
IOCBP
INTCON
PIE1
PIE2
PIR1
PIR2
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used in Power-down
Instruction Flow
(INTCON reg.)
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
execution of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
and postscaler (if enabled) will be cleared, the TO
bit will be set and the PD bit will be cleared.
(INTCON reg.)
Note
INTF flag
GIE bit
Instruction
Fetched
Instruction
Executed
OSC1
CLKOUT
INT pin
1:
2:
3:
4:
Wake-up Using Interrupts
PC
(1)
mode.
TMR1GIE
TMR1GIF
XT, HS or LP Oscillator mode assumed.
T
GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.
CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.
(4)
IOCBN7
IOCBP7
IOCBF7
OST
OSFIE
OSFIE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC) = Sleep
Bit 7
GIE
Inst(PC - 1)
= 1024 T
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC
IOCBF6
IOCBN6
IOCBP6
PEIE
ADIE
ADIF
Bit 6
C2IE
C2IE
(drawing not to scale). This delay does not apply to EC and RC Oscillator modes.
Inst(PC + 1)
Sleep
PC + 1
IOCBN5
IOCBP5
TMR0IE
IOCBF5
RCIE
RCIF
Bit 5
C1IE
C1IE
Processor in
Sleep
IOCBN4
IOCBF4
IOCBP4
PC + 2
INTE
TXIE
EEIE
EEIE
Bit 4
TXIF
Preliminary
T
OST (2)
IOCBF3
IOCBN3
IOCBP3
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPIE
BCLIE
SSPIF
BCLIE
IOCIE
Bit 3
Interrupt Latency
Inst(PC + 2)
Inst(PC + 1)
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
PC + 2
IOCBN2
IOCBP2
IOCBF2
TMR0IF
CCP1IE
CCP1IF
LCDIE
LCDIE
Bit 2
(3)
Dummy Cycle
PC + 2
IOCBN1
IOCBF1
IOCBP1
TMR2IE
TMR2IF
INTF
Bit 1
—
—
© 2009 Microchip Technology Inc.
Dummy Cycle
Inst(0004h)
0004h
IOCBN0
IOCBF0
IOCBP0
TMR1IE
CCP2IE
TMR1IF
CCP2IE
IOCIF
Bit 0
Inst(0005h)
Inst(0004h)
Register on
0005h
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